M
Moritz Beller
Guest
Hello,
I want to construct an array consisting of 4 rows with 8 columns,
every single cell reprensenting a byte of 8 bits, given by
reg [7:0] expandedkey [8:0][3:0];
reg [7:0] cipherstate [8:0][3:0];
(1) Is this syntheziable Verilog code? Are the rows/columns in order?
(2) Is
function [7:0] AddRoundKey [8:0][3:0];
input [7:0] value1 [8:0][3:0];
AddRoundKey = value1 ^ cipherstate;
endfunction
a valid function then, making cipherstate = AddRoundKey(expandedkey) a
correct assignment?
best regards
Moritz Beller
--
web http://www.4momo.de
mail momo dot beller at t-online dot de
gpgkey http://gpg.notlong.com
I want to construct an array consisting of 4 rows with 8 columns,
every single cell reprensenting a byte of 8 bits, given by
reg [7:0] expandedkey [8:0][3:0];
reg [7:0] cipherstate [8:0][3:0];
(1) Is this syntheziable Verilog code? Are the rows/columns in order?
(2) Is
function [7:0] AddRoundKey [8:0][3:0];
input [7:0] value1 [8:0][3:0];
AddRoundKey = value1 ^ cipherstate;
endfunction
a valid function then, making cipherstate = AddRoundKey(expandedkey) a
correct assignment?
best regards
Moritz Beller
--
web http://www.4momo.de
mail momo dot beller at t-online dot de
gpgkey http://gpg.notlong.com