array

D

daniele

Guest
hello everybody, i have the necessity to use an array of
std_logic_vector's, and i would like to do it in such a way that both
the size of the array and the size of the std_logic_vector be defined
by generic parameters.

i tried the following code, inside an architecture:

signal wires : array (0 to num) of std_logic_vector(width downto 0);

but it seems not to work.
a way to "almost" solve the problem would be to define, in a package, a
type in this way:

type wires is array (natural range <>) of std_logic_vector (width
downto 0);

but the problem is that, being the definition inside a package, i
cannot define "width" as a generic...

does anybody know whether there's a way to do it?

thanx in advance,
daniele
 
daniele a écrit :
hello everybody, i have the necessity to use an array of
std_logic_vector's, and i would like to do it in such a way that both
the size of the array and the size of the std_logic_vector be defined
by generic parameters.

i tried the following code, inside an architecture:
signal wires : array (0 to num) of std_logic_vector(width downto 0);
but it seems not to work.
Click to expand...
Hi
You can not do it this way but you're pretty close.
You have to define an array type:
type wire_array is array(natural range <>) of
std_logic_vector(width-1 downto 0);
and then you can declare your signal
signal wires : wire_array(0 to num);

Nicolas
 
Hi, thanx for your help, but with your solution I still can't specify
the dimension of the std_logic_vector (i.e. the value of "width" in
your example) when i make the declaration

signal wires : wire_array(0 to num);

is there a way to do it?

thanx everybody,
daniele
 
daniele wrote:
Hi, thanx for your help, but with your solution I still can't specify
the dimension of the std_logic_vector (i.e. the value of "width" in
your example) when i make the declaration
signal wires : wire_array(0 to num);
is there a way to do it?
Click to expand...
I would use the packaged values as the *default*
value for the generics.

entity foo is
generic (
num_g : natural := packaged_num_c;
width_g : natural := packaged_width_c)
...

-- Mike Treseler
 
daniele a écrit :
Hi, thanx for your help, but with your solution I still can't specify
the dimension of the std_logic_vector (i.e. the value of "width" in
your example) when i make the declaration

signal wires : wire_array(0 to num);

is there a way to do it?
Click to expand...
As far as I know, no. You can only do it when declaring the array type.

Nicolas
 
Nicolas Matringe wrote:

As far as I know, no. You can only do it when declaring the array type.
Click to expand...
Yes, the generic/packaged constants
are used to declare types that
are used to declare variables/signals.

-- Mike Treseler
 
Daniele
Right now, you can't do it the way you want to.
Next language revision = Accellera VHDL-2006 will have this.

For now you have to linearize your matrix and then
extract your information from it:
signal wires : std_logic_vector( 0 to (num+1)*(width+1)-1) ;

Cheers,
Jim

hello everybody, i have the necessity to use an array of
std_logic_vector's, and i would like to do it in such a way that both
the size of the array and the size of the std_logic_vector be defined
by generic parameters.

i tried the following code, inside an architecture:

signal wires : array (0 to num) of std_logic_vector(width downto 0);

but it seems not to work.
a way to "almost" solve the problem would be to define, in a package, a
type in this way:

type wires is array (natural range <>) of std_logic_vector (width
downto 0);

but the problem is that, being the definition inside a package, i
cannot define "width" as a generic...

does anybody know whether there's a way to do it?

thanx in advance,
daniele
Click to expand...

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
This is how I create RAM models, and sounds like what you are trying to
do:

type RAM is array (0 to 2**Addr_Width - 1) of
std_logic_vector(Data_Width - 1 downto 0);
signal RAM_Array : RAM;

Addr_Width and Data_Width are both constants, and are used to specify
both this vector, and several of the I/O vectors. Specifically:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity GEN_Dual_Port_RAM is
generic (
Data_Width : natural := 32;
Addr_Width : natural := 6
);
port
(
Clock : in std_logic;

Write_Address : in
std_logic_vector(Addr_Width - 1 downto 0);
Write_Enable : in std_logic;
Write_Data : in
std_logic_vector(Data_Width - 1 downto 0);

Read_Address : in
std_logic_vector(Addr_Width - 1 downto 0);
Read_Data : out
std_logic_vector(Data_Width - 1 downto 0)
);

end GEN_Dual_Port_RAM;

architecture rtl of GEN_Dual_Port_RAM is

constant HIGH : std_logic := '1';
constant LOW : std_logic := '0';
constant HIZ : std_logic := 'Z';

type RAM is array (0 to 2**Addr_Width - 1) of
std_logic_vector(Data_Width - 1 downto 0);
signal RAM_Array : RAM;

begin

Read_Data <=
RAM_Array(CONV_INTEGER(Read_Address));

RAM_Update: process(Clock)
begin
if (Clock'EVENT and Clock = HIGH) then
if( Write_Enable = HIGH ) then
RAM_Array(CONV_INTEGER(Write_Address)) <= Write_Data;
end if;
end if;
end process RAM_Update;

end rtl;
 
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