J
jin
Guest
I need to generate a set of array signal from a vector, see below:
input:
config_clock : in std_logic_vector(24 downto 1);
internal signal array:
type chain_array is array (24 downto 1) of std_logic_vector(24 downto
1);
signal clock_chain_mask : chain_array;
the process is to generate 24*24 mask signal, if I define 24 signal
like:
signal clock_chain_mask_1 : std_logic_vector(24 downto 1);
signal clock_chain_mask_2 : std_logic_vector(24 downto 1);
....
....
signal clock_chain_mask_24 : std_logic_vector(24 downto 1);
then call 24 processes like:
U1: process ( config_clock(1))
variable j; --j is valid from 1 to 24
...
... clock_chain_mask_1(j) <= '1';
end process U1;
U2: process ( config_clock(2))
variable j;
...
... clock_chain_mask_1(j) <= '1';
end process U2;
This works fine. If I change data structure to array, like:
U1: process ( config_clock(1))
variable j;
...
... clock_chain_mask(j)(1) <= '1';
end process U1;
U2: process ( config_clock(2))
variable j;
...
... clock_chain_mask(j)(2) <= '1';
end process U2;
the clock_chain_mask array cannot ouput any signal. I am wondering if
the array signal can be assigned in process like this way. Thanks.
input:
config_clock : in std_logic_vector(24 downto 1);
internal signal array:
type chain_array is array (24 downto 1) of std_logic_vector(24 downto
1);
signal clock_chain_mask : chain_array;
the process is to generate 24*24 mask signal, if I define 24 signal
like:
signal clock_chain_mask_1 : std_logic_vector(24 downto 1);
signal clock_chain_mask_2 : std_logic_vector(24 downto 1);
....
....
signal clock_chain_mask_24 : std_logic_vector(24 downto 1);
then call 24 processes like:
U1: process ( config_clock(1))
variable j; --j is valid from 1 to 24
...
... clock_chain_mask_1(j) <= '1';
end process U1;
U2: process ( config_clock(2))
variable j;
...
... clock_chain_mask_1(j) <= '1';
end process U2;
This works fine. If I change data structure to array, like:
U1: process ( config_clock(1))
variable j;
...
... clock_chain_mask(j)(1) <= '1';
end process U1;
U2: process ( config_clock(2))
variable j;
...
... clock_chain_mask(j)(2) <= '1';
end process U2;
the clock_chain_mask array cannot ouput any signal. I am wondering if
the array signal can be assigned in process like this way. Thanks.