Array Ports

[Bill Burris]

What is the syntax for arrays as ports?

In the following code ModelSim says: Illegal reference to net array "dbin".

module Chan_MUX ( clk, select, dbin, dbout );

parameter db_width = 16;
parameter channels = 8;

input clk;
input [4:0] select;
input [db_width-1:0] dbin [channels-1:0];
output [db_width-1:0] dbout;

reg [db_width-1:0] dbout;

always @(posedge clk)
begin
dbout <= dbin[select];
end

endmodule


thanks
Bill

 

[Dwayne Dilbeck]

IEEE1364-2001 declares it illegal to use arrays as ports. See the section
of the formal syntax below.

With that said some tools will accept it. ModelSim obviously won't.
Cadence's IUS won't, Cadence's HDL-ICE(for emulation) will synthesize it.
But it transforms the illegal code into a legal form.

ie: input [3:0] DBA [0:4] ; becomes input [0:19] DBA


If you are going to pass arrays you will need to transform them into 1-d
vectors before you can use them,

ie: input [width-1:0] ex1 [0:depth-1] becomes input [0:width*depth -1] ex1;



A.2.1.2 Port declarations

inout_declaration ::= inout [ net_type ] [ signed ] [ range ]

list_of_port_identifiers

input_declaration ::= input [ net_type ] [ signed ] [ range ]

list_of_port_identifiers

output_declaration ::=

output [ net_type ] [ signed ] [ range ]

list_of_port_identifiers

| output [ reg ] [ signed ] [ range ]

list_of_port_identifiers

| output reg [ signed ] [ range ]

list_of_variable_port_identifiers

| output [ output_variable_type ]

list_of_port_identifiers

| output output_variable_type

list_of_variable_port_identifiers


"Bill Burris" <wburris@ualberta.ca> wrote in message
news:fmoj45$jbr$1@tabloid.srv.ualberta.ca...

What is the syntax for arrays as ports?

In the following code ModelSim says: Illegal reference to net array
"dbin".

module Chan_MUX ( clk, select, dbin, dbout );

parameter db_width = 16;
parameter channels = 8;

input clk;
input [4:0] select;
input [db_width-1:0] dbin [channels-1:0];
output [db_width-1:0] dbout;

reg [db_width-1:0] dbout;

always @(posedge clk)
begin
dbout <= dbin[select];
end

endmodule


thanks
Bill

 

[gtwrek@pacbell.net]

On Jan 17, 1:59 pm, Bill Burris <wbur...@ualberta.ca> wrote:

What is the syntax for arrays as ports?

In the following code ModelSim says: Illegal reference to net array "dbin".

module Chan_MUX ( clk, select, dbin, dbout );

parameter db_width = 16;
parameter channels = 8;

input clk;
input [4:0] select;
input [db_width-1:0] dbin [channels-1:0];
output [db_width-1:0] dbout;

Bill,

It's legal in SystemVerilog - which Modelsim supports
(just add -sv your vlog command line).

If you can't use SystemVerilog, then you're stuck
making concatenated long vectors.

Regards,

Mark

 

[gtwrek@pacbell.net]

On Jan 17, 3:00 pm, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote:

IEEE1364-2001 declares it illegal to use arrays as ports. See the section
of the formal syntax below.

With that said some tools will accept it. ModelSim obviously won't.
Cadence's IUS won't, Cadence's HDL-ICE(for emulation) will synthesize it.
But it transforms the illegal code into a legal form.

ie: input [3:0] DBA [0:4] ; becomes input [0:19] DBA

Dwayne,

Wow, I never knew of any tool that did this.
I don't believe this is standard in
any way is it?

SystemVerilog does standardize the conversion
of PACKED arrays to long wires (and
vice versa). But unpacked conversions (which is what
these basically are), are undefined.


--Mark

 

[Dwayne Dilbeck]

It is WAY outside of standard, definitely a hybrid. I wouldn't have
expected it myself if I hadn't tried it. Of coarse, most of the time the
HDL-ICE tool is much more restrictive than IUS, since you are synthesizing
to a model for an emulator(timing doesn't matter and generates
errors/warnings).


<gtwrek@pacbell.net> wrote in message
news:6ffbef08-c3bd-4b33-9c54-9a18d8d597cc@e6g2000prf.googlegroups.com...

On Jan 17, 3:00 pm, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote:
IEEE1364-2001 declares it illegal to use arrays as ports. See the
section
of the formal syntax below.

With that said some tools will accept it. ModelSim obviously won't.
Cadence's IUS won't, Cadence's HDL-ICE(for emulation) will synthesize
it.
But it transforms the illegal code into a legal form.

ie: input [3:0] DBA [0:4] ; becomes input [0:19] DBA


Dwayne,

Wow, I never knew of any tool that did this.
I don't believe this is standard in
any way is it?

SystemVerilog does standardize the conversion
of PACKED arrays to long wires (and
vice versa). But unpacked conversions (which is what
these basically are), are undefined.


--Mark

 

[Bill Burris]

It's legal in SystemVerilog - which Modelsim supports
(just add -sv your vlog command line).

Thanks Mark

I also need to synthesize my design in Altera Quartus II. For other
projects I use Xilinx ISE. For some strange reason the docs on these
tools don't make it easy to find what standards they support.

Bill