H
hssig
Guest
Hi,
I want to declare an array "vecarr " which consists of
std_logic_vector, and a second
array "arr3d " to pipeline the first array.
When simuating the following test code Modelsim complains:
** Fatal: (vsim-3734) Index value 0 is out of range 4 downto 1.
------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity arr_pipe is
end entity;
architecture xy of arr_pipe is
type t_vecarr is array(natural range <>
of std_logic_vector(7 downto
0);
signal vecarr : t_vecarr(15 downto 0) := (others => (others => '1'));
type t_arr3d is array(natural range <>
of t_vecarr(15 downto 0);
signal arr3d : t_arr3d(4 downto 0);
signal clk : std_logic;
begin
process
begin
clk <= '1'; wait for 5 ns;
clk <= '0'; wait for 5 ns;
end process;
process(clk)
begin
if rising_edge(clk) then
for m in 0 to 15 loop
arr3d(arr3d'high)(m) <= vecarr(m);
arr3d(arr3d'high-1 downto 0)(m) <= arr3d(arr3d'high
downto 1)(m); --** ERROR
end loop;
end if;
end process;
end xy;
------------------------------------------------------------------------------------------------
Can someone explain to me what is wrong about that shift register ?
Cheers,
hssig
I want to declare an array "vecarr " which consists of
std_logic_vector, and a second
array "arr3d " to pipeline the first array.
When simuating the following test code Modelsim complains:
** Fatal: (vsim-3734) Index value 0 is out of range 4 downto 1.
------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity arr_pipe is
end entity;
architecture xy of arr_pipe is
type t_vecarr is array(natural range <>
0);
signal vecarr : t_vecarr(15 downto 0) := (others => (others => '1'));
type t_arr3d is array(natural range <>
signal arr3d : t_arr3d(4 downto 0);
signal clk : std_logic;
begin
process
begin
clk <= '1'; wait for 5 ns;
clk <= '0'; wait for 5 ns;
end process;
process(clk)
begin
if rising_edge(clk) then
for m in 0 to 15 loop
arr3d(arr3d'high)(m) <= vecarr(m);
arr3d(arr3d'high-1 downto 0)(m) <= arr3d(arr3d'high
downto 1)(m); --** ERROR
end loop;
end if;
end process;
end xy;
------------------------------------------------------------------------------------------------
Can someone explain to me what is wrong about that shift register ?
Cheers,
hssig