Array of reals?

[Russell Fredrickson]

Hi all,

Is there any way to declare an array of reals in verilog? I tried the
following:

real RealArray [1:REAL_ARRAY_DEPTH];

and came up with a syntax error in ncverilog. Should I be declaring this a
different way? From my research before this post it looks like I could use
the $realtobits and the $bitstoreal tasks to work around this limitation (by
then using a regular array).

Thanks in advance,
Russell Fredrickson

 

[Steven Sharp]

"Russell Fredrickson" <russell_fredrickson@hp.com> wrote in message news:<bi5tmf$d9s$1@news.vcd.hp.com>...

Is there any way to declare an array of reals in verilog? I tried the
following:

real RealArray [1:REAL_ARRAY_DEPTH];

and came up with a syntax error in ncverilog.

Arrays of reals were not allowed in Verilog-1995. They were added in
Verilog-2001, but are not supported in NC-Verilog yet. Compared to the
other extensions in Verilog-2001, they are pretty low priority. We have
had no customer requests for them.

Multi-dimensional arrays of regs will be supported in the next release,
currently in beta. Work on arrays of nets has started. I wouldn't
expect arrays of reals or named events to be supported before those are
done. If arrays of reals are important to you, you can make a request
for them and we will take that into account in our priorities.

From my research before this post it looks like I could use
the $realtobits and the $bitstoreal tasks to work around this limitation (by
then using a regular array).

Yes, you could declare an array of 64-bit vectors and use $realtobits
and $bitstoreal to convert between reals and their bit-equivalent for
storage. It is inconvenient, but should work.