array of module instances

[sridhar]

The following compiles fine, but I am getting an error when I try to
simulate(using aldec hdl6.2).

module x;
parameter n = 3;
wire [num:0]a1,a2,a3;
//this is where the problem comes
and a[num:0](a1,{a2[num-1:0],1'b1},{a3[num-1:0],1'b1});
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
endmodule
Is this allowed?
TIA
-sridhar

 

[jools]

No. The array or bus indices have to real integers already defined values,
ie before simulation.

"sridhar" <v_sridhar@mailcity.com> wrote in message
news:7492ef5f.0402251743.631fbbd8@posting.google.com...

The following compiles fine, but I am getting an error when I try to
simulate(using aldec hdl6.2).

module x;
parameter n = 3;
wire [num:0]a1,a2,a3;
//this is where the problem comes
and a[num:0](a1,{a2[num-1:0],1'b1},{a3[num-1:0],1'b1});
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
endmodule
Is this allowed?
TIA
-sridhar

 

[Steven Sharp]

v_sridhar@mailcity.com (sridhar) wrote in message news:<7492ef5f.0402251743.631fbbd8@posting.google.com>...

The following compiles fine, but I am getting an error when I try to
simulate(using aldec hdl6.2).

module x;
parameter n = 3;
wire [num:0]a1,a2,a3;
//this is where the problem comes
and a[num:0](a1,{a2[num-1:0],1'b1},{a3[num-1:0],1'b1});
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
endmodule
Is this allowed?

You are referring to "num", which is not defined anywhere. I assume
that your parameter "n" was supposed to be named "num". I don't
know whether this is a typo inserted during posting, or if it is
the cause of the problem you are seeing.

Assuming that you make num a parameter, and therefore constant,
this code should be legal. The ranges in the declarations and
in the part selects are all constant expressions, so they should
be fine. The code runs under both Verilog-XL and NC-Verilog.

 

[sridhar]

sharp@cadence.com (Steven Sharp) wrote in message news:<3a8e124e.0402261122.6a4a7f5f@posting.google.com>...

v_sridhar@mailcity.com (sridhar) wrote in message news:<7492ef5f.0402251743.631fbbd8@posting.google.com>...
The following compiles fine, but I am getting an error when I try to
simulate(using aldec hdl6.2).

module x;
parameter n = 3;
wire [num:0]a1,a2,a3;
//this is where the problem comes
and a[num:0](a1,{a2[num-1:0],1'b1},{a3[num-1:0],1'b1});
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
endmodule
Is this allowed?

You are referring to "num", which is not defined anywhere. I assume
that your parameter "n" was supposed to be named "num". I don't
know whether this is a typo inserted during posting, or if it is
the cause of the problem you are seeing.

Assuming that you make num a parameter, and therefore constant,
this code should be legal. The ranges in the declarations and
in the part selects are all constant expressions, so they should
be fine. The code runs under both Verilog-XL and NC-Verilog.

Sorry, that was a typo. Thanks for thinking through the mistake and
clarifying it.As I said, it compiles fine but when I try to simulate
it points out some error which I guess is a problem with the tool!
Thanks
sridhar