A
Ayoub
Guest
Hi everybody !
I want to add(xor) data with CD in shape array and the result would be S
Can you help me correcting this code :
""""
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cdm is
--generic (
-- width : natural :=4);
port (
clk : in std_logic ;
rst : in std_logic ;
data: in std_logic ;
odata: out std_logic ;
CD : in std_logic_vector(15 downto 0) ;
isis
ut integer range 0 to 15 ;
S : inout std_logic_vector(3 downto 0 ));
end entity ;
architecture beh of cdm is
type tab is array(3 downto 0)of std_logic_vector(15 downto 0);
signal i :integer range 0 to 15 ;
signal idata :std_logic ;
signal itab :tab ;
begin
code
rocess(clk,rst)
begin
if(rst='1')then
itab(i)<="0000" ;
else
if(clk'event and clk='1')then
S(i)<=(CD(i) xor (data));
i<= i+1 ;
if i=15 then
idata<=data ;
end if ;
end if ;
end if ;
end process ;
isis<=i;
odata<=idata ;
end architecture ; ""
Thank you in advance for your answer !!!^^
I want to add(xor) data with CD in shape array and the result would be S
Can you help me correcting this code :
""""
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cdm is
--generic (
-- width : natural :=4);
port (
clk : in std_logic ;
rst : in std_logic ;
data: in std_logic ;
odata: out std_logic ;
CD : in std_logic_vector(15 downto 0) ;
isis
S : inout std_logic_vector(3 downto 0 ));
end entity ;
architecture beh of cdm is
type tab is array(3 downto 0)of std_logic_vector(15 downto 0);
signal i :integer range 0 to 15 ;
signal idata :std_logic ;
signal itab :tab ;
begin
code
begin
if(rst='1')then
itab(i)<="0000" ;
else
if(clk'event and clk='1')then
S(i)<=(CD(i) xor (data));
i<= i+1 ;
if i=15 then
idata<=data ;
end if ;
end if ;
end if ;
end process ;
isis<=i;
odata<=idata ;
end architecture ; ""
Thank you in advance for your answer !!!^^