Array of interface

[Rich.]

Hi,

anyone knows if it is possible to define an array of interface inside
a module in systemverilog?

i.e.

interface my_if;
...
endinterface

module my_module;

my_if my_if_arr()[n]; // Well, this is not how it's done....
...
endmodule

 

[Rich.]

I got it...

This is the syntax.

my_if my_if_arr[n]();

/Rich.