array of instances

[paz]

Hi,


Does anyone know how array of instance works in verilog?

For example:

I found an example like this:

wire[2:0] in;
wire[2:0] out;
wire ctrl;

bufif0 u[2:0] (out, in, ctrl);

I read that Each primitive instantiation is done separately, and
actually this equals to:

bufif0 u2 (out[2], in[2], ctrl);
bufif0 u1 (out[1], in[1], ctrl);
bufif0 u0 (out[0], in[0], ctrl);

How does verilog "know" to divide out to 3 for 3 instances, but to
connect all instances to ctrl (which is only one bit)?

How does it work?

 

IME, Verilog "sign extends" to fill. That is, the highest order bit is
replicated in the remaining positions. (It may replicate, but in this
example, there is no difference.)

ctrl can be though of as ctrl[0:0]. So where it "wanted" bits 2 and 1,
the "MSB" of ctrl[0:0] (aka ctrl) is connected.

(If it replicates, the intermediate term would be
{ctrl[0:0],ctrl[0:0],ctrl[0:0]}.)

Hope that helps,
GH


paz wrote:

Hi,


Does anyone know how array of instance works in verilog?

For example:

I found an example like this:

wire[2:0] in;
wire[2:0] out;
wire ctrl;

bufif0 u[2:0] (out, in, ctrl);

I read that Each primitive instantiation is done separately, and
actually this equals to:

bufif0 u2 (out[2], in[2], ctrl);
bufif0 u1 (out[1], in[1], ctrl);
bufif0 u0 (out[0], in[0], ctrl);

How does verilog "know" to divide out to 3 for 3 instances, but to
connect all instances to ctrl (which is only one bit)?

How does it work?

 

[dbwalker0min@gmail.com]

The rules for instance array connects (taken from the Verilog LRM)...

The terminal connections for an array of instances shall follow these
rules:

1) The bit length of each port expression in the declared
instance-array shall be compared with the bit length of each
single-instance port or terminal in the instantiated module or
primitive.
2) For each port or terminal where the bit length of the instance-array
port expression is the same as the bit length of the single-instance
port, the instance-array port expression shall be connected to each
single-instance port.
3) If bit lengths are different, each instance shall get a part-select
of the port expression as specified in the range, starting with the
right-hand index.

Too many or too few bits to connect to all the instances shall be
considered an error.

David Walker

ghelbig@lycos.com wrote:

IME, Verilog "sign extends" to fill. That is, the highest order bit is
replicated in the remaining positions. (It may replicate, but in this
example, there is no difference.)

ctrl can be though of as ctrl[0:0]. So where it "wanted" bits 2 and 1,
the "MSB" of ctrl[0:0] (aka ctrl) is connected.

(If it replicates, the intermediate term would be
{ctrl[0:0],ctrl[0:0],ctrl[0:0]}.)

Hope that helps,
GH


paz wrote:
Hi,


Does anyone know how array of instance works in verilog?

For example:

I found an example like this:

wire[2:0] in;
wire[2:0] out;
wire ctrl;

bufif0 u[2:0] (out, in, ctrl);

I read that Each primitive instantiation is done separately, and
actually this equals to:

bufif0 u2 (out[2], in[2], ctrl);
bufif0 u1 (out[1], in[1], ctrl);
bufif0 u0 (out[0], in[0], ctrl);

How does verilog "know" to divide out to 3 for 3 instances, but to
connect all instances to ctrl (which is only one bit)?

How does it work?

 

[paz]

Thanks a lot!


dbwalker0min@gmail.com ëúá:

The rules for instance array connects (taken from the Verilog LRM)...

The terminal connections for an array of instances shall follow these
rules:

1) The bit length of each port expression in the declared
instance-array shall be compared with the bit length of each
single-instance port or terminal in the instantiated module or
primitive.
2) For each port or terminal where the bit length of the instance-array
port expression is the same as the bit length of the single-instance
port, the instance-array port expression shall be connected to each
single-instance port.
3) If bit lengths are different, each instance shall get a part-select
of the port expression as specified in the range, starting with the
right-hand index.

Too many or too few bits to connect to all the instances shall be
considered an error.

David Walker

ghelbig@lycos.com wrote:
IME, Verilog "sign extends" to fill. That is, the highest order bit is
replicated in the remaining positions. (It may replicate, but in this
example, there is no difference.)

ctrl can be though of as ctrl[0:0]. So where it "wanted" bits 2 and 1,
the "MSB" of ctrl[0:0] (aka ctrl) is connected.

(If it replicates, the intermediate term would be
{ctrl[0:0],ctrl[0:0],ctrl[0:0]}.)

Hope that helps,
GH


paz wrote:
Hi,


Does anyone know how array of instance works in verilog?

For example:

I found an example like this:

wire[2:0] in;
wire[2:0] out;
wire ctrl;

bufif0 u[2:0] (out, in, ctrl);

I read that Each primitive instantiation is done separately, and
actually this equals to:

bufif0 u2 (out[2], in[2], ctrl);
bufif0 u1 (out[1], in[1], ctrl);
bufif0 u0 (out[0], in[0], ctrl);

How does verilog "know" to divide out to 3 for 3 instances, but to
connect all instances to ctrl (which is only one bit)?

How does it work?