Array of generic width std_logic_vector in entity?

[Brandon]

From reading old posts, I see it is not possible to have an array of
generic-width std_logic_vector in an entity. I've seen some of the work

arounds, including using the type std_logic_matrix, but I'm not
entirely happy with them (none of them are straightforward).

Are there any plans to allow unconstrained arrays to have unconstrained
elements? Something like...

type arrayofstdlv_t is array (natural range<&gt of std_logic_vector;

Such that, I could have an entity like,

entity myentity is
generic (
depth: integer;
width: integer
port (
x : in arrayofstdlv_t(depth-1 downto 0)(width-1 downto 0);
...
);
end entity myentity;

I'm trying to implement something like this now, and I really don't
want to unwrap a generic array of std_logic_vector's to one long
generic depth*width length vector to implement it.

What does everyone else do in practice for writing generic models?

 

[Brandon]

I'm not worried about using old synthesis tools...

Yes, I understand this is possible, but it's not as clean as I would
like. In a simulation environment a long vector like that doesn't
convey any information in a straightforward way. For example, I might
have an array of length 32 of std_logic_vector(15 downto 0) for a total
of 512 bits, which represent 32 numeric inputs. In a testbench I
typically display these ports in hex and if they are fixed-point
numbers, I'll have a conversion entity to translate that fixed-point
number to floating point for visual inspection and verification.

But like I said, I can't create an array of unconstrained vectors,
which I find to be somewhat limiting. Is the 1-d vector technique the
typical workaround? In the end we're still talking the same number of
bits, it's just the syntax of the model in question.