array of components

[The Weiss Family]

Hi All,

I want to create an array of components that I can use an index to access.
I am aware of the "generate" statement, but I don't know if I can do what I
need.

I need to have non-array signals used in the port map.
This is probably best explained by an example:

------------------------------------------------------------------
component my_component is
port (
A : in std_logic;
B : in std_logic;
C : out std_logic);
end my_component;


--- somewhere in another entity
signal u,v,w,x,y,z : std_logic;

COMP0: my_component port map(
A=>x,
B=>y,
C=>z);

COMP1: my_component port map(
A=>u,
B=>v,
C=>w);
-------------------------------------------------------------------

The problem is that I would like some structure that I can index by 0 to
access COMP0 and by 1 to access COMP1.
For example:

my_comp(0).some_function;
my_comp(1).some_constant;

etc....

Any ideas?

Thanks

 

[Jim Lewis]

You are thinking in terms of Verilog and complicating
the picture. In Verilog subprograms have static variables
and are not reentrant. Hence you keep them in a module
and only call them once. Note this changed for some classes
of subprograms in Verilog 2001, however, I am not sure of the
details.


In VHDL, all subprograms are reentrant. We put them
in a package and reference them as often as we wish.
A package is very similar to a compiled ".h" file that
has a particular syntax. We also define constants in
the packages that we want to share amoung multiple
designs. You will note for referencing subprograms
from packages, we include a use clause and we can reference
the subprogram by its simple name:
Y <= some_function(..) ;


So in VHDL there is no reason to do the following, hence,
there is no mechanism that allows you to do it.
my_comp(0).some_function
my_comp(1).some_constant


As you explore VHDL further, read about
subprogram overloading and the use of unconstrained
arrays on inputs. These are both some of VHDLs
cool features.


If you want to instantiate multiple components, you can
either do it the way you did. Note, the component
instances go in the same architecture that has the
component declaration. To emphasize this, I added the
rest of the architecture below. You can also use
"for generate" to do the component instantiation, but
it is not necessary in such a simple case as below.


architecture structural of mydes is

component my_component is
port (
A : in std_logic;
B : in std_logic;
C : out std_logic);
end my_component;

--- must be in the same architecture

signal u,v,w,x,y,z : std_logic;

Begin

COMP0: my_component port map(
A=>x,
B=>y,
C=>z);

COMP1: my_component port map(
A=>u,
B=>v,
C=>w);
end structural ;

Cheers,
Jim

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~