Array input problem

[thomasc]

I need to pass an array to a module from a higher level module. But as long
as I know, it is not allowed in Verilog.
Is there any typical way to pass an array as an input to a module(such as
using loop)?

Thank you!

 

[Paul Uiterlinden]

thomasc wrote:

I need to pass an array to a module from a higher level module. But as long
as I know, it is not allowed in Verilog.
Is there any typical way to pass an array as an input to a module(such as
using loop)?

http://www.google.com/groups?as_q=pass%20array%20module&as_ugroup=comp.lang.verilog&lr=&hl=nl

 

[glen herrmannsfeldt]

thomasc wrote:

I need to pass an array to a module from a higher level module. But as long
as I know, it is not allowed in Verilog.
Is there any typical way to pass an array as an input to a module(such as
using loop)?

What hardware function are you trying to design. That should
give a hint as to how you should pass the array.

Imagine building your system out of 74xx TTL gates, what would
your array look like?

-- glen