Array Assignement in System Verilog

[sghosh]

Here is a code snipet from System verilog array assignment.

module test(out1, in1);
input [3:0] in1;
output reg [9:0] out1;

bit signed [1:0] mem1[1:0];
bit signed [2:0] mem [1:0];

always @*
begin
mem1[1] = in1[3:2];
mem1[0] = in1[1:0];
mem = mem1;
out1 = mem[1];
end

Is the assignment mem=mem1 permitted under SV array assignment rules.
Here unpacked dimension and size are same in both array, but packed
size
is different,

Thanks in advance!

Subhankar

 

[Swapnajit Mittra]

VCS 7.1.1 apparently allows it (with +v2k and +sysvcs
options). Depending on simulator YMMV.

- Swapnajit.
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