arithmentic and logic shift: does 'signed' help?

[Andy Luotto]

Hello, I am designing a digital block using signed arithmetic. I
wonder how Verilog / Verilog 2K / System Verilog and I am using the
signed

wire signed [REZ-1+DITHER+GUARD:0] un;

This works
assign un = wn - enm1*2 + enm1/128;

This DOES NOT work

assign un = wn - (enm1<<1) + (enm1>>7);

because it performs a LOGICAL shift. How do I implement arithmetich
shifts in verilog? I was thinking that this is done automatically as
long as the shifts are applied to signed wires or regs

thanks for discussing this

 

[dbwalker0min@gmail.com]

In standard Verilog, there is no way to do an arithmetic shift. In
Verilog 2K and SystemVerilog, use the operators "<<<" or ">>>" for an
arithmetic shift.

David Walker
On Mar 28, 9:07 am, "Andy Luotto" <andyluo...@excite.com> wrote:

Hello, I am designing a digital block using signed arithmetic. I
wonder how Verilog / Verilog 2K / System Verilog and I am using the
signed

wire signed [REZ-1+DITHER+GUARD:0] un;

This works
assign un = wn - enm1*2 + enm1/128;

This DOES NOT work

assign un = wn - (enm1<<1) + (enm1>>7);

because it performs a LOGICAL shift. How do I implement arithmetich
shifts in verilog? I was thinking that this is done automatically as
long as the shifts are applied to signed wires or regs

thanks for discussing this

 

Andy Luotto wrote:

Hello, I am designing a digital block using signed arithmetic. I
wonder how Verilog / Verilog 2K / System Verilog and I am using the
signed

wire signed [REZ-1+DITHER+GUARD:0] un;

This works
assign un = wn - enm1*2 + enm1/128;

This DOES NOT work

assign un = wn - (enm1<<1) + (enm1>>7);

because it performs a LOGICAL shift. How do I implement arithmetich
shifts in verilog? I was thinking that this is done automatically as
long as the shifts are applied to signed wires or regs

The old Verilog shift operators >> and << always did logical shifts,
even when applied to integers, which were signed. For backward
compatibility, they had to continue doing logical shifts, even when
applied to signed operands.

So Verilog-2001 added new shift operators >>> and <<<. These
are sometimes called the arithmetic shift operators, which is a
misnomer. They do an arithmetic shift when applied to signed
operands, but a logical shift when applied to unsigned operands.
So they do what you expected the old shift operators to do.

Note that <<< is no different from <<, since there is no difference
between logical and arithmetic on a left shift. It is just provided
so your code can look more consistent, using >>> and <<<
everywhere.

Note also that if there are any unsigned operands in the context
of the shift subexpression, that this will make the shift operand
unsigned before the shift. Avoid mixing signed and unsigned
operands in an expression unless you fully understand the
rules involved.