Area

[bir]

What are the ways we can reduce the area of a design ??

Thanks

 

[Rajkumar Kadam]

Hi!
Few consideration for reducing area of the design
1. Optimal micro-architecture
2. Running design at lower speed, if possible.
3. Representing design in RTL appropriately.
4. Using low speed library
5. Providing realistics constraints
6. To some extent Verifying the tool output at different stages,
(maybe required)

Rajkumar...


bir wrote:

What are the ways we can reduce the area of a design ??

Thanks

 

[mk]

On 29 Nov 2006 22:59:13 -0800, "Rajkumar Kadam"
<shubamshreyas@yahoo.com> wrote:

Hi!
Few consideration for reducing area of the design
4. Using low speed library

Actually this would be probably counterproductive. All other things
being equal a lower speed library would tighten the constraints and
would force the synthesizer to generate a larger area design to meet
timing.
The best way to reduce area is resource reuse assuming you can afford
the time to do the multiplexing or doing things serially. In control
logic this usually means programmable control logic or programmable
state machines as opposed to hardwired ones ie a very basic
micro-controller which looks at different inputs and switches its
logic based on which group of inputs its considering can replace
multiple control blocks or state machines. In datapath it means you
need to reuse the datapath blocks. Use an adder over multiple cycles
to do a multiplication instead of a parallel multiplier. Use a single
multiplier in a multiply-add instead of several multipliers and
multi-input adder, use one full-adder which cycles over individual
bits of input vectors to do an add instead of several full adders.
These all reduce the throughput you can get from from your design but
at a much lower area cost.

 

[bir]

Thanks for all those replies.

I am designing a debug subsystem which basically helps devices which
are JTAG compliant to access the system bus and do all kind of memory
upload & download operation. From the rtl perspective, I used aroung
850 flops in my design and my total area is something around 17000.
Considering this this to be larger than my expectations, I tried
numerous means to bring it down, but the difference is very
minor(around couple of hundred). I removed all the timing constraints
to give to make the area as the priority but still no result.

Any suggestions.


Thanks


mk wrote:

On 29 Nov 2006 22:59:13 -0800, "Rajkumar Kadam"
shubamshreyas@yahoo.com> wrote:

Hi!
Few consideration for reducing area of the design
4. Using low speed library

Actually this would be probably counterproductive. All other things
being equal a lower speed library would tighten the constraints and
would force the synthesizer to generate a larger area design to meet
timing.
The best way to reduce area is resource reuse assuming you can afford
the time to do the multiplexing or doing things serially. In control
logic this usually means programmable control logic or programmable
state machines as opposed to hardwired ones ie a very basic
micro-controller which looks at different inputs and switches its
logic based on which group of inputs its considering can replace
multiple control blocks or state machines. In datapath it means you
need to reuse the datapath blocks. Use an adder over multiple cycles
to do a multiplication instead of a parallel multiplier. Use a single
multiplier in a multiply-add instead of several multipliers and
multi-input adder, use one full-adder which cycles over individual
bits of input vectors to do an add instead of several full adders.
These all reduce the throughput you can get from from your design but
at a much lower area cost.

 

[John_H]

If you have Synplify(Pro), for instance, you can look at the
rpt_designname.areasrr to see how many resources are needed for your
hierarchical blocks. If you have 850 flops for your logic and you think it
should use significantly less, this will tell you where your logic expands
beyond your expectations.


"bir" <ritwikbiswas@gmail.com> wrote in message
news:1165001045.657431.290160@n67g2000cwd.googlegroups.com...

Thanks for all those replies.

I am designing a debug subsystem which basically helps devices which
are JTAG compliant to access the system bus and do all kind of memory
upload & download operation. From the rtl perspective, I used aroung
850 flops in my design and my total area is something around 17000.
Considering this this to be larger than my expectations, I tried
numerous means to bring it down, but the difference is very
minor(around couple of hundred). I removed all the timing constraints
to give to make the area as the priority but still no result.

Any suggestions.


Thanks

 

[dbwalker0min@gmail.com]

Is it an ASIC or FPGA? If it is an ASIC, what process are you using? If
it is an FPGA, I'm guessing the 17,000 number is the number of CLBs?

David Walker

bir wrote:

Thanks for all those replies.

I am designing a debug subsystem which basically helps devices which
are JTAG compliant to access the system bus and do all kind of memory
upload & download operation. From the rtl perspective, I used aroung
850 flops in my design and my total area is something around 17000.
Considering this this to be larger than my expectations, I tried
numerous means to bring it down, but the difference is very
minor(around couple of hundred). I removed all the timing constraints
to give to make the area as the priority but still no result.

Any suggestions.


Thanks


mk wrote:
On 29 Nov 2006 22:59:13 -0800, "Rajkumar Kadam"
shubamshreyas@yahoo.com> wrote:

Hi!
Few consideration for reducing area of the design
4. Using low speed library

Actually this would be probably counterproductive. All other things
being equal a lower speed library would tighten the constraints and
would force the synthesizer to generate a larger area design to meet
timing.
The best way to reduce area is resource reuse assuming you can afford
the time to do the multiplexing or doing things serially. In control
logic this usually means programmable control logic or programmable
state machines as opposed to hardwired ones ie a very basic
micro-controller which looks at different inputs and switches its
logic based on which group of inputs its considering can replace
multiple control blocks or state machines. In datapath it means you
need to reuse the datapath blocks. Use an adder over multiple cycles
to do a multiplication instead of a parallel multiplier. Use a single
multiplier in a multiply-add instead of several multipliers and
multi-input adder, use one full-adder which cycles over individual
bits of input vectors to do an add instead of several full adders.
These all reduce the throughput you can get from from your design but
at a much lower area cost.