T
tulip
Guest
hello,
I have 3 component instatiation statements
r1: srt port map(gate1,set1,reset1,C,one,H1);
r2: str port map(gate2,set2,reset2,H1,H1,H2);
r3: str port map(gate3,set3,reset3,H2,H2,Hout);
The first 3 parameters in the component instatiation statement represent
Gate, Set and Reset signals respectively. 3rd and 4th parameters are the
inputs and the 5th parameter is the output of the component str.
I wrote the architectureand gave the Gate, Set and Reset signals such
that the 1st component r1 is enabled in the first clock cycle , the 2nd
component r2 in the 2nd clock cycle and the 3rd component r3 in the 3rd
clock cycle.
Three separate str components r1, r2 and r3 are used by these 3
statements. But I want my architecture to be area optimized so that only 1
str architecture is used by all these 3 component instantiation statements
one after the other.
Can anyone suggest in this regard.
I have 3 component instatiation statements
r1: srt port map(gate1,set1,reset1,C,one,H1);
r2: str port map(gate2,set2,reset2,H1,H1,H2);
r3: str port map(gate3,set3,reset3,H2,H2,Hout);
The first 3 parameters in the component instatiation statement represent
Gate, Set and Reset signals respectively. 3rd and 4th parameters are the
inputs and the 5th parameter is the output of the component str.
I wrote the architectureand gave the Gate, Set and Reset signals such
that the 1st component r1 is enabled in the first clock cycle , the 2nd
component r2 in the 2nd clock cycle and the 3rd component r3 in the 3rd
clock cycle.
Three separate str components r1, r2 and r3 are used by these 3
statements. But I want my architecture to be area optimized so that only 1
str architecture is used by all these 3 component instantiation statements
one after the other.
Can anyone suggest in this regard.