Area constraint on a sub-module

[Ramtilak]

Hi,

Can anyone suggest how to assign a area constraint on a sub-module
within my design? I dont care where the other sub-modules are as long
as this particular sub-module is in the required area. I know we can
assign a area constraint for the whole design. But, how to do it for a
sub-module?

Thanks in advance,
Ramtilak

 

[Jim Wu]

Ramtilak wrote:

Hi,

Can anyone suggest how to assign a area constraint on a sub-module
within my design? I dont care where the other sub-modules are as long
as this particular sub-module is in the required area. I know we can
assign a area constraint for the whole design. But, how to do it for a
sub-module?

For Xilinx FPGA and tools, add something like below to the ucf file:

INST “hierarchy/path/to/submodule” AREA_GROUP = "your_area_group_name";
AREA_GROUP “your_area_group_name” RANGE = range;

HTH,
Jim (jimwu88NOOOSPAM@yahoo.com remve NOOOSPAM)
http://www.geocities.com/jimwu88/chips

 

[Cody]

remember to check the KEEP_HIERARCHY in the XST Options, and put
AREA_GROUP “your_area_group_name” PLACE = CLOSED;
AREA_GROUP “your_area_group_name” GROUP = CLOSED;

Kelvin





"Jim Wu" <NOSPAM@NOSPAM.COM> wrote in message
news:fujLc.30825$F8.15097@nwrdny02.gnilink.net...

Ramtilak wrote:
Hi,

Can anyone suggest how to assign a area constraint on a sub-module
within my design? I dont care where the other sub-modules are as long
as this particular sub-module is in the required area. I know we can
assign a area constraint for the whole design. But, how to do it for a
sub-module?

For Xilinx FPGA and tools, add something like below to the ucf file:

INST “hierarchy/path/to/submodule” AREA_GROUP = "your_area_group_name";
AREA_GROUP “your_area_group_name” RANGE = range;

HTH,
Jim (jimwu88NOOOSPAM@yahoo.com remve NOOOSPAM)
http://www.geocities.com/jimwu88/chips

 

[Yttrium]

or you could use the incremental design flow

http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/xst/xst0035_6.html

"Cody" <cody1980@hotmail.com> wrote in message
news:40fdd0d6@news.starhub.net.sg...

remember to check the KEEP_HIERARCHY in the XST Options, and put
AREA_GROUP "your_area_group_name" PLACE = CLOSED;
AREA_GROUP "your_area_group_name" GROUP = CLOSED;

Kelvin





"Jim Wu" <NOSPAM@NOSPAM.COM> wrote in message
news:fujLc.30825$F8.15097@nwrdny02.gnilink.net...


Ramtilak wrote:
Hi,

Can anyone suggest how to assign a area constraint on a sub-module
within my design? I dont care where the other sub-modules are as long
as this particular sub-module is in the required area. I know we can
assign a area constraint for the whole design. But, how to do it for a
sub-module?

For Xilinx FPGA and tools, add something like below to the ucf file:

INST "hierarchy/path/to/submodule" AREA_GROUP = "your_area_group_name";
AREA_GROUP "your_area_group_name" RANGE = range;

HTH,
Jim (jimwu88NOOOSPAM@yahoo.com remve NOOOSPAM)
http://www.geocities.com/jimwu88/chips