area constrains in UCF (or PACE)

[Yttrium]

hey, for now i just use

AREA_GROUP "AreaGroupName" RANGE = SLICE_X0Y79:SLICE_X27Y54 ;
INST "/" AREA_GROUP = " AreaGroupName " ;

as area constraint but i can't really find how you can place your individual
components?

let's say you have a root component A which is composed by components B and
C how can you say that you want

B in the range X0Y0:X10Y10
C in the range X11Y0:X20Y10
and if possible A in the range X0Y0:X30Y30

i thought it should be something like

INST "/B" ... or INST "/A/B"... but it all gives an error ...

btw i'm using xst (ise6.1) ...

thanx in advance for you comments,

kind regards,

Y

 

[Philip Freidin]

On Sat, 28 Feb 2004 13:19:13 GMT, "Yttrium" <Yttrium@pandora.be> wrote:

hey, for now i just use

AREA_GROUP "AreaGroupName" RANGE = SLICE_X0Y79:SLICE_X27Y54 ;
INST "/" AREA_GROUP = " AreaGroupName " ;

as area constraint but i can't really find how you can place your individual
components?

let's say you have a root component A which is composed by components B and
C how can you say that you want

B in the range X0Y0:X10Y10
C in the range X11Y0:X20Y10
and if possible A in the range X0Y0:X30Y30

i thought it should be something like

INST "/B" ... or INST "/A/B"... but it all gives an error ...

btw i'm using xst (ise6.1) ...

thanx in advance for you comments,

kind regards,

Y

You may want to read:

http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/cgd/cgd0058_11.html

but more importantly:

http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/cgd/cgd0028_6.html

and

http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/cgd/cgd0128_81.html

The key to your problem is that the INST object selector selects primitive
objects such as gates, flipflops, memories, I/O . It does not select clouds
of logic, such as a section of HDL hierarchy.

When synthesis processes your HDL, it turns it into named gates, ff, ....
but these named items are not predictable, so even if you read the netlist
(EDIF) (Which XST stupidly does not make available anymore), you would have
to create an INST line for each gate, FF, ... . And then when you
re-synthesize, all these names would change if you made any change to your
source code.

The situation is not hopeless though. As you will see in the second reference
above, you are allowed to use the "*" wild card.

So ....

let's say you have a root component A which is composed by components B and
C how can you say that you want

B in the range X0Y0:X10Y10
C in the range X11Y0:X20Y10
and if possible A in the range X0Y0:X30Y30

The doc says that the top level is ignored:
"Top-level block names (design names) are ignored when searching for instance name matches."

INST "B/*" LOC = SLICE_X0Y0:SLICE_X10Y10;
INST "C/*" LOC = SLICE_X11Y0:SLICE_X20Y10;

I don't think another costraint that specifies your top level block "*" and
constains to X0Y0:X30Y30 is going to help you, as it will also apply this
constraint to the B and C block as well as to the desired stuff that is in A
but not B or C. You may have to take this A logic and put it in a new
sub block D, which could be constrained to the overlapping region X0Y0:X30Y30 .

You will note that the above examples did not require AREA_GROUPS, but
could have been rewritten to use that form.

I don't guarantee that the above is correct, but I think it should be a good
direction for you to proceed.

Philip




===================
Philip Freidin
philip@fliptronics.com
Host for WWW.FPGA-FAQ.COM

 

[Brian Davis]

Philip wrote :

but these named items are not predictable, so even if you read the netlist
(EDIF) (Which XST stupidly does not make available anymore)

Although not perfect, NGC2EDIF works well enough to unravel any XST net
renaming, inspect user applied attributes, etc.

http://www.fpga-faq.com/archives/58175.html#58181

Brian

p.s. Thanks for your effort in maintaining the fpga-faq archive and
board list, those fpga-faq links are much shorter than google's