Are Verilog tasks reentrant?

[Raymond Bingham]

I'm not sure reentrant is the right term, but I have two initial
blocks that call the same task, possibly at the same time. It appears
that the second alters the "input" signal for the first. Is this a
feature of Verilog or what?

--Ray

 

[Jon Beniston]

rbingham@dotcast.com (Raymond Bingham) wrote in message news:<c26550fd.0409151304.129ab6a1@posting.google.com>...

I'm not sure reentrant is the right term, but I have two initial
blocks that call the same task, possibly at the same time. It appears
that the second alters the "input" signal for the first. Is this a
feature of Verilog or what?

Verilog tasks are not reentrant.

Cheers,
JonB

 

[Chris Alexander]

I am not sure if the standard is specific about this or not, but the
behavior you describe is the way I have always seen it work (with both
Cadence and Synopsys tools).

I seem to recall being able to get around this by copy/pasting with
uniquified names so that there is a separate task for targeting
different targets:

task write_reg1;
task body only interfaces to reg1
....

task write_reg2;
task body only interfaces to reg2
....

rbingham@dotcast.com (Raymond Bingham) wrote in message news:<c26550fd.0409151304.129ab6a1@posting.google.com>...

I'm not sure reentrant is the right term, but I have two initial
blocks that call the same task, possibly at the same time. It appears
that the second alters the "input" signal for the first. Is this a
feature of Verilog or what?

--Ray

 

[Chris Briggs]

rbingham@dotcast.com (Raymond Bingham) wrote in message news:<c26550fd.0409151304.129ab6a1@posting.google.com>...

I'm not sure reentrant is the right term, but I have two initial
blocks that call the same task, possibly at the same time. It appears
that the second alters the "input" signal for the first. Is this a
feature of Verilog or what?

Yes, "reentrant" is the right word. Reentrant tasks and functions were
not supported in the Verilog-1995 spec, but they are supported in the
Verilog-2001 spec. You have to put the word "automatic" after the word
"task" or "function" to declare a task/function as reentrant.

Whether you can use them depends on whether your simulator supports
this Verilog-2001 feature. Check your simulator docs, check Cliff
Cummings' Verilog-2001 scoreboard, or just try it and see if it
compiles.

-cb