Are there any tools convert verilog netlist to data dependen

Hi,
I'm now working on a project that need analyze the synthesised netlist.

Are there any tool can take verilog netlist as input , and generate a DDG which vertices are registers and edges are combinational logic?

Many thanks,
Stanley

 

[Nikolaos Kavvadias]

Dear Stanley

I don't think that niche tool exists. I personally have not heard of a dependency extractor for XNF, EDIF or another netlist format.

However, you should have a look at the YOSYS logic synthesis engine. This looks very good and I known that it uses Graphviz graphs to visualize netlists. So maybe there might be a dependency extractor somewhere in the sources..

http://clifford.at/yosys/

Best regards
Nikolaos Kavvadias
http://www.nkavvadias.com


Τη Πέμπτη, 13 Μαρτίου 2014 10:13:39 π.μ. UTC+2, ο χρήστης stanle...@gmail.com έγραψε:

Hi,

I'm now working on a project that need analyze the synthesised netlist..



Are there any tool can take verilog netlist as input , and generate a DDG which vertices are registers and edges are combinational logic?



Many thanks,

Stanley

 

[Stephen Williams]

On 03/13/2014 01:13 AM, stanley79830@gmail.com wrote:

Hi,
I'm now working on a project that need analyze the synthesised netlist.

Are there any tool can take verilog netlist as input , and generate a DDG which vertices are registers and edges are combinational logic?

You can probably get a lot of what you need by using the ivl_target.h
API of Icarus Verilog. See <http://iverilog.icarus.com> and also the
iverilog-devel mailing list.



--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."