Are there any resources talking about verification on the WE

[Peng Yu]

Hi,
In particular, I want some resoures for writing testbench for a
sequenctial verilog description. I know there two books from the FAQ,
which are "Writing testbenches: Functional Verification of HDL Models"
and "Principles of Verifiable RTL Design". But they aren't at my hand
right now. Could somebody introduce some more resources for me?
Thanks!
Peng

 

[VhdlCohen]

Checkout veriflang.pdf Document: Transaction-Based Verification in HDL
Available at my site, under Models and Papers.
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------