Architecture name through hierarchy

Hello all.

I'm having trouble with my implementation (it's actually VHDL-AMS, but I think my issue does not come from th "-AMS" part).

Here is what I am trying to do :
- I have a testbench file, in which I instanciate a top module.
- In this top module, I instanciate a couple of smaller modules, including one containing many different architectures.

I want to chose the implemented architecture thanks to an argument specified in the testbench file.

What I tried :
- in the testbench file, declaring a string matching one of the architecture and sending it to the top module as a generic.
- in the top module, I created a generic string and used it to instanciate my smaller module.

With some extremely simplified code :

-- test bench --
[...]
ARCHTECTURE beh OF tb_top is
[...]
system : ENTITY top(beh)
GENERIC MAP("arch_name") -- arch_name is a real architecture name of module
[...]

-- top --
ENTITY top IS
GENERIC(example : string)
[...]
ARCHITECTURE beh OF top IS
[...]
module_1 : ENTITY module(example)
[...]

I can compile my different files just fine, but when I try to simulate, the software cannot build my system, and tells me that the architecture example of module does not exist. And it is correct : it is the architecture arch_name I want to use. But it seems the argument cannot go all the way through the hierarchy.

Do you know :
1- if it is doable ?
2- what the syntax is ?

Thank you in advance.

Basil1402

 

[Blaise Mulliez]

I just tried and made the argument a PORT (as a SIGNAL).
Still the same : can compile, but not simulate.

On Tuesday, April 2, 2013 11:12:10 AM UTC+2, Blaise Mulliez wrote:

Hello all.



I'm having trouble with my implementation (it's actually VHDL-AMS, but I think my issue does not come from th "-AMS" part).



Here is what I am trying to do :

- I have a testbench file, in which I instanciate a top module.

- In this top module, I instanciate a couple of smaller modules, including one containing many different architectures.



I want to chose the implemented architecture thanks to an argument specified in the testbench file.



What I tried :

- in the testbench file, declaring a string matching one of the architecture and sending it to the top module as a generic.

- in the top module, I created a generic string and used it to instanciate my smaller module.



With some extremely simplified code :



-- test bench --

[...]

ARCHTECTURE beh OF tb_top is

[...]

system : ENTITY top(beh)

GENERIC MAP("arch_name") -- arch_name is a real architecture name of module

[...]



-- top --

ENTITY top IS

GENERIC(example : string)

[...]

ARCHITECTURE beh OF top IS

[...]

module_1 : ENTITY module(example)

[...]



I can compile my different files just fine, but when I try to simulate, the software cannot build my system, and tells me that the architecture example of module does not exist. And it is correct : it is the architecture arch_name I want to use. But it seems the argument cannot go all the way through the hierarchy.



Do you know :

1- if it is doable ?

2- what the syntax is ?



Thank you in advance.



Basil1402

 

[KJ]

Unless something changed with VHDL-2008, what you're doing won't work. The architecture name has to be literally typed in, it is not in any way a variable that you can select.

What you can do though is instantiate both each inside a generate statement and have the testbench select which one to use like this...

Gen_If_Arch_1 : if (Arch = 1) generate -- Whatever condition you want to use here
begin
-- Instantiate the entity/architecture here
end Gen_If_Arch_1;

Gen_If_Arch_2 : if (Arch = 2) generate -- Whatever condition you want to use here
begin
-- Instantiate the entity/architecture here
end Gen_If_Arch_2;

Kevin Jennings

 

[Blaise Mulliez]

Ok, thanks for the hint.

I tried what you said, but I cannot make that generate statement work with a the specification of an particular architecture.

I wrote :

gen_module : if (arch_nb=1)
GENERATE
inst_module : module(arch_module)
PORT MAP(...);
END GENERATE gen_module;

When I try to compile, I am said :
[Error]Unexpected parenthesis: module should be a procedure name.

I guess my syntax is wrong somewhere. But I cannot find how to write it right.

Can you help me ?

Thanks in advance.

On Tuesday, April 2, 2013 12:59:20 PM UTC+2, KJ wrote:

Unless something changed with VHDL-2008, what you're doing won't work. The architecture name has to be literally typed in, it is not in any way a variable that you can select.



What you can do though is instantiate both each inside a generate statement and have the testbench select which one to use like this...



Gen_If_Arch_1 : if (Arch = 1) generate -- Whatever condition you want to use here

begin

-- Instantiate the entity/architecture here

end Gen_If_Arch_1;



Gen_If_Arch_2 : if (Arch = 2) generate -- Whatever condition you want to use here

begin

-- Instantiate the entity/architecture here

end Gen_If_Arch_2;



Kevin Jennings

 

[Basil1402]

My bad, I just forgot the "ENTITY" keyword.

Now, I have a AMS specific question (dunno if someone can help me).

When I do not use the Generate statement (but directly instanciate a component, I have no compilation issue.

But if I do use a Generate statement, the compiler tells me that "the characteristic number (3) does not match the number of scalar equations (2) [LRM section 12.6.6]". It seems it does not count the output of the Generate block as an equation.

Any idea ?


On Tuesday, April 2, 2013 2:15:19 PM UTC+2, Basil1402 wrote:

Ok, thanks for the hint.



I tried what you said, but I cannot make that generate statement work with a the specification of an particular architecture.



I wrote :



gen_module : if (arch_nb=1)

GENERATE

inst_module : module(arch_module)

PORT MAP(...);

END GENERATE gen_module;



When I try to compile, I am said :

[Error]Unexpected parenthesis: module should be a procedure name.



I guess my syntax is wrong somewhere. But I cannot find how to write it right.



Can you help me ?



Thanks in advance.



On Tuesday, April 2, 2013 12:59:20 PM UTC+2, KJ wrote:

Unless something changed with VHDL-2008, what you're doing won't work. The architecture name has to be literally typed in, it is not in any way a variable that you can select.







What you can do though is instantiate both each inside a generate statement and have the testbench select which one to use like this...







Gen_If_Arch_1 : if (Arch = 1) generate -- Whatever condition you want to use here



begin



-- Instantiate the entity/architecture here



end Gen_If_Arch_1;







Gen_If_Arch_2 : if (Arch = 2) generate -- Whatever condition you want to use here



begin



-- Instantiate the entity/architecture here



end Gen_If_Arch_2;







Kevin Jennings

 

[Thomas Stanka]

Am Dienstag, 2. April 2013 11:12:10 UTC+2 schrieb Basil1402:

I want to chose the implemented architecture thanks to an argument specified in the testbench file.
[..]
What I tried :

- in the testbench file, declaring a string matching one of the architecture and sending it to the top module as a generic.

- in the top module, I created a generic string and used it to instanciate my smaller module.

What you should have tried is using of configurations.
You can configure in your testbench all architectures you like to use.

YOu have the choice to create alternative configurations for each architecture and use on toplevel either conf_A or conf_B of next deeper level, or you could use nested configuration:

[code simplified and therefore not syntactical correct]
For testbench
for topmodule
for memory use configuration_brandX;
end for
end for

bye Thomas

 

[KJ]

On Wednesday, April 3, 2013 5:20:41 AM UTC-4, Thomas Stanka wrote:

What you should have tried is using of configurations. You can configure in
your testbench all architectures you like to use. YOu have the choice to
create alternative configurations for each architecture and use on toplevel
either conf_A or conf_B of next deeper level, or you could use nested
configuration

Just a note, that if you go this route, you cannot use direct entity instantiation. You can only configure components so you would need to create component declarations. Not a big deal, but a difference to note.

Kevin