Arbiter

I am designing a bit arbiter with following behavior:

Request(0 to 3): 0000 1010 0110 1101 0010 1001 0001 1000 1011 1011
1000 0101 1001
Reset
HHHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHHHLLLLLLLLLLLLLLLLLL
Ack(0 to 3): 0000 1000 0010 0100 0010 1000 0001 1000 0000 1000
1000 0100 0001

There is a reset line that's active high and if high, it will set all
the Ack(0 to 3) to 0000. The current Request(0 to 3) compares to the
previous Request(0 to 3) to see if there were bits that were requested
earlier but were not acknowledged on Ack(0 to 3) and it gives them
priority in the current Ack(0 to 3).

I hope I explained ok here. I'm having trouble putting this behavior
into codes in VHDL. Someone has any idea?

 

[Eric Smith]

willwestward@gmail.com writes:

I hope I explained ok here. I'm having trouble putting this behavior
into codes in VHDL. Someone has any idea?

How would you design it with logic gates (and flip-flops, if required)?

Once you know that, you can just do the same thing in VHDL.