Arbiter for the wishbone bus

[Pooja]

Hi everyone,

I have two "blocks" accessing the same wishbone bus, and hence I am
writing an arbiter which would allow access to only one of the masters
at a time. I do have a simple implementation of an arbiter, but what I
don't get is: which signals do I need in order to "enable" one of the
two masters on the wishbone bus.

Thanks in advance for any help.

 

[Mark McDougall]

Pooja wrote:

I have two "blocks" accessing the same wishbone bus, and hence I am
writing an arbiter which would allow access to only one of the masters
at a time. I do have a simple implementation of an arbiter, but what I
don't get is: which signals do I need in order to "enable" one of the
two masters on the wishbone bus.

There's an example of an arbiter in the rev B.1 wishbone specification
itself. Rev B.3 has a different treatment.

In a nutshell, you just need a mux for the master outputs (CYC_O, STB_O,
ADR_O, DAT_O, WE_O) whose selector is the output of your arbitrator
algorithm. Similarly, your selector also determines which master
receives the ACK_O/ERR_O/RTY_O from the slave. So you're not 'enabling'
one master as such, simply gating the slave response so that only the
master which has been granted the bus sees the end of the cycle.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266