K
Kelvin @ SG
Guest
Hi, there:
I have found that Xilinx synthesis directive "mult_style =lut" can only be
applied to either a reg/wire directly under a module, or applied to the
module itself.
A complicated design or module may contain multipliers wrapped in
a task or function, in which situation I may or may not define a wire/reg.
I have discovered that mult_style didn't work in either a function or a task.
The use of mult_style on the module itself applies to ALL the multiplers
in the module irregardless of whether a multiplier is wrapped in a function/
task or not.
so, how do I constrain "mult_style =lut" on my multiplier in a function/task
statement while leave my bare multipliers to BLOCK alone?
Thanks.
Kelvin
I have found that Xilinx synthesis directive "mult_style =lut" can only be
applied to either a reg/wire directly under a module, or applied to the
module itself.
A complicated design or module may contain multipliers wrapped in
a task or function, in which situation I may or may not define a wire/reg.
I have discovered that mult_style didn't work in either a function or a task.
The use of mult_style on the module itself applies to ALL the multiplers
in the module irregardless of whether a multiplier is wrapped in a function/
task or not.
so, how do I constrain "mult_style =lut" on my multiplier in a function/task
statement while leave my bare multipliers to BLOCK alone?
Thanks.
Kelvin