API calls in Verilog

[deepak]

Currently i use a test bench file which is read when i run my
simulation

read_file = $fopen("abcd.cfg", "r"); and i have the file abcd.cfg
being read.

However i need to make this a dynamic process where instead of
abcd.cfg , I should be able to pass a filename which is obtained from
the command line and isn't hardcoded as a specific filename. Is there
any specific mechanism via say an API call which does this ??

 

[Guenter Dannoritzer]

deepak wrote:

Currently i use a test bench file which is read when i run my
simulation

read_file = $fopen("abcd.cfg", "r"); and i have the file abcd.cfg
being read.

However i need to make this a dynamic process where instead of
abcd.cfg , I should be able to pass a filename which is obtained from
the command line and isn't hardcoded as a specific filename. Is there
any specific mechanism via say an API call which does this ??

Usually your simulator allows you to define macros with the command line
call. So you can define a macro with the simulator call and use that
macro in the Verilog code as file name.

Cheers,

Guenter

 

[Ryan]

A macro will just replace one fixed file name with another. Use $value
$plusargs(user_string, variable) to get a runtime command line
argument.

reg [8*32:1] test;
if (! $value$plusargs("TEST=%s",test)) begin
$display("You must supply a test!");
$finish;
end
read_file = $fopen(test, "r");

Then run like:

simv +TEST=abcd.cfg


See the IEEE 1364-2001 LRM (and most simulator docs) for more
examples.

Ryan

On Dec 7, 9:13 am, Guenter Dannoritzer <kratfkryk...@spammotel.com>
wrote:

deepak wrote:
Currently i use a test bench file which is read when i run my
simulation

read_file = $fopen("abcd.cfg", "r"); and i have the file abcd.cfg
being read.

However i need to make this a dynamic process where instead of
abcd.cfg , I should be able to pass a filename which is obtained from
the command line and isn't hardcoded as a specific filename. Is there
any specific mechanism via say an API call which does this ??

Usually your simulator allows you to define macros with the command line
call. So you can define a macro with the simulator call and use that
macro in the Verilog code as file name.

Cheers,

Guenter