AoE3 D-flips and glitches

[George Herold]

As part of reintroducing myself to digital electronics,
I've been reading chapter 10 of AoE3. My question regards the footnote
(60) on page 738. Fig 10.73 shows how a rising edge D-FF can make a glitch.
Putting an inverter in the clk line might make a glitch at the leading edge..
(if the D-flip is faster than the inverter.) So the rather obvious answer
is to stick the inverter before the clock input of the D-flip.. giving
two propagation delays in that section.... Is that the "right" answer?

Tia
George H.

 

[George Herold]

On Tuesday, January 19, 2016 at 4:23:33 PM UTC-5, Tim Wescott wrote:

On Tue, 19 Jan 2016 10:23:19 -0800, George Herold wrote:

As part of reintroducing myself to digital electronics,
I've been reading chapter 10 of AoE3. My question regards the footnote
(60) on page 738. Fig 10.73 shows how a rising edge D-FF can make a
glitch. Putting an inverter in the clk line might make a glitch at the
leading edge..
(if the D-flip is faster than the inverter.) So the rather obvious
answer is to stick the inverter before the clock input of the D-flip..
giving two propagation delays in that section.... Is that the "right"
answer?

Tia George H.

Post an ASCII-art schematic? I don't think I have revision 3.

--
www.wescottdesign.com

Gotta run Tim... I was thinking I should snap a picture of the page,
and post it. Perhaps tonight.

George H.

 

[Tim Wescott]

On Tue, 19 Jan 2016 10:23:19 -0800, George Herold wrote:

As part of reintroducing myself to digital electronics,
I've been reading chapter 10 of AoE3. My question regards the footnote
(60) on page 738. Fig 10.73 shows how a rising edge D-FF can make a
glitch. Putting an inverter in the clk line might make a glitch at the
leading edge..
(if the D-flip is faster than the inverter.) So the rather obvious
answer is to stick the inverter before the clock input of the D-flip..
giving two propagation delays in that section.... Is that the "right"
answer?

Tia George H.

Post an ASCII-art schematic? I don't think I have revision 3.

--
www.wescottdesign.com

 

[George Herold]

On Tuesday, January 19, 2016 at 4:23:33 PM UTC-5, Tim Wescott wrote:

On Tue, 19 Jan 2016 10:23:19 -0800, George Herold wrote:

As part of reintroducing myself to digital electronics,
I've been reading chapter 10 of AoE3. My question regards the footnote
(60) on page 738. Fig 10.73 shows how a rising edge D-FF can make a
glitch. Putting an inverter in the clk line might make a glitch at the
leading edge..
(if the D-flip is faster than the inverter.) So the rather obvious
answer is to stick the inverter before the clock input of the D-flip..
giving two propagation delays in that section.... Is that the "right"
answer?

Tia George H.

Post an ASCII-art schematic? I don't think I have revision 3.

--
www.wescottdesign.com

No third edition? Treat yourself and spend the money.
Here's a picture from Aoe3
https://www.dropbox.com/s/66qxydq710bjjgg/pg738.JPG?dl=0

I've got a similar little glitch in my circuit. A D-flip turns off with the rising
edge of the clock pulse, that goes to a Nand gate, but doesn't get there in time to
turn off the gate before a little bit of the (same) clk edge gets through.

It's at the end after all the counting is done and doesn't have any effect...
Still (according to H&H) it's bad form.

Here it is..
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0

Ch1 is the clock
Ch2 is the output pulse (negative true)
C3 is the signal after the Nand gate that goes to the counters.

Here's a pic where I'm clocking at 1 MHz... so you can see clk and glitch.
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0

Hey, Maybe if instead of gating the clock I can just disable the counter...

Have I said lately how much I like talking to you guys... even when you're silent
you still give me ideas :^)

Cheers,
George H.

 

[George Herold]

On Wednesday, January 20, 2016 at 2:59:39 PM UTC-5, George Herold wrote:

On Tuesday, January 19, 2016 at 4:23:33 PM UTC-5, Tim Wescott wrote:
On Tue, 19 Jan 2016 10:23:19 -0800, George Herold wrote:

As part of reintroducing myself to digital electronics,
I've been reading chapter 10 of AoE3. My question regards the footnote
(60) on page 738. Fig 10.73 shows how a rising edge D-FF can make a
glitch. Putting an inverter in the clk line might make a glitch at the
leading edge..
(if the D-flip is faster than the inverter.) So the rather obvious
answer is to stick the inverter before the clock input of the D-flip..
giving two propagation delays in that section.... Is that the "right"
answer?

Tia George H.

Post an ASCII-art schematic? I don't think I have revision 3.

--
www.wescottdesign.com

No third edition? Treat yourself and spend the money.
Here's a picture from Aoe3
https://www.dropbox.com/s/66qxydq710bjjgg/pg738.JPG?dl=0

I've got a similar little glitch in my circuit. A D-flip turns off with the rising
edge of the clock pulse, that goes to a Nand gate, but doesn't get there in time to
turn off the gate before a little bit of the (same) clk edge gets through.

It's at the end after all the counting is done and doesn't have any effect...
Still (according to H&H) it's bad form.

Here it is..
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0

Ch1 is the clock
Ch2 is the output pulse (negative true)
C3 is the signal after the Nand gate that goes to the counters.

Here's a pic where I'm clocking at 1 MHz... so you can see clk and glitch.
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0

dang wrong pic again... sorry,
https://www.dropbox.com/s/frz91exmlbvwluf/TEK0001.BMP?dl=0
better.

Hey, Maybe if instead of gating the clock I can just disable the counter...

Have I said lately how much I like talking to you guys... even when you're silent
you still give me ideas :^)

Cheers,
George H.

 

[Jim Thompson]

On Tue, 19 Jan 2016 10:23:19 -0800 (PST), George Herold
<gherold@teachspin.com> wrote:

As part of reintroducing myself to digital electronics,
I've been reading chapter 10 of AoE3. My question regards the footnote
(60) on page 738. Fig 10.73 shows how a rising edge D-FF can make a glitch.
Putting an inverter in the clk line might make a glitch at the leading edge..
(if the D-flip is faster than the inverter.) So the rather obvious answer
is to stick the inverter before the clock input of the D-flip.. giving
two propagation delays in that section.... Is that the "right" answer?

Tia
George H.

You're missing the point... doodle out a timing diagram.

The trailing AND gate avoids the glitch.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[George Herold]

On Wednesday, January 20, 2016 at 5:38:45 PM UTC-5, Tim Wescott wrote:

On Wed, 20 Jan 2016 11:59:36 -0800, George Herold wrote:

On Tuesday, January 19, 2016 at 4:23:33 PM UTC-5, Tim Wescott wrote:
On Tue, 19 Jan 2016 10:23:19 -0800, George Herold wrote:

As part of reintroducing myself to digital electronics,
I've been reading chapter 10 of AoE3. My question regards the
footnote (60) on page 738. Fig 10.73 shows how a rising edge D-FF
can make a glitch. Putting an inverter in the clk line might make a
glitch at the leading edge..
(if the D-flip is faster than the inverter.) So the rather obvious
answer is to stick the inverter before the clock input of the
D-flip.. giving two propagation delays in that section.... Is that
the "right" answer?

Tia George H.

Post an ASCII-art schematic? I don't think I have revision 3.

--
www.wescottdesign.com

No third edition? Treat yourself and spend the money.
Here's a picture from Aoe3
https://www.dropbox.com/s/66qxydq710bjjgg/pg738.JPG?dl=0

I've got a similar little glitch in my circuit. A D-flip turns off with
the rising edge of the clock pulse, that goes to a Nand gate, but
doesn't get there in time to turn off the gate before a little bit of
the (same) clk edge gets through.

It's at the end after all the counting is done and doesn't have any
effect... Still (according to H&H) it's bad form.

Here it is..
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0

Ch1 is the clock Ch2 is the output pulse (negative true)
C3 is the signal after the Nand gate that goes to the counters.

Here's a pic where I'm clocking at 1 MHz... so you can see clk and
glitch. https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0

Hey, Maybe if instead of gating the clock I can just disable the
counter...

Have I said lately how much I like talking to you guys... even when
you're silent you still give me ideas :^)

OK. So it's not the flip-flop that's causing the glitch -- it's trying
to use the output of the flip-flop to turn a clock on and off that's
causing the glitch. That makes sense.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

It's OK I got rid of the glitch by getting rid of the AND gate
(nand in my case)
I use the D flip to enable the counter skipping the redundant AND gate.
The counter down counts and when it gets to the end, it turns off
a S/R which is feed to the D input of the D-flip. It seems
like a clean loop now.
I'm not very good at digital... I don't do it often enough.

I wanted to say, I didn't want to do this project.
But once I mentioned it, I felt obligated to finish it up..
(a good thing.)
Hey, there's got to be a pcb soon. I had this
crazy idea of laying out the IC's so that I could stick
in DIP's and later smd's onto the same board spin.
(Assuming the pin-out matches up..
I better check..
later

George H.

 

[Tim Wescott]

On Wed, 20 Jan 2016 11:59:36 -0800, George Herold wrote:

On Tuesday, January 19, 2016 at 4:23:33 PM UTC-5, Tim Wescott wrote:
On Tue, 19 Jan 2016 10:23:19 -0800, George Herold wrote:

As part of reintroducing myself to digital electronics,
I've been reading chapter 10 of AoE3. My question regards the
footnote (60) on page 738. Fig 10.73 shows how a rising edge D-FF
can make a glitch. Putting an inverter in the clk line might make a
glitch at the leading edge..
(if the D-flip is faster than the inverter.) So the rather obvious
answer is to stick the inverter before the clock input of the
D-flip.. giving two propagation delays in that section.... Is that
the "right" answer?

Tia George H.

Post an ASCII-art schematic? I don't think I have revision 3.

--
www.wescottdesign.com

No third edition? Treat yourself and spend the money.
Here's a picture from Aoe3
https://www.dropbox.com/s/66qxydq710bjjgg/pg738.JPG?dl=0

I've got a similar little glitch in my circuit. A D-flip turns off with
the rising edge of the clock pulse, that goes to a Nand gate, but
doesn't get there in time to turn off the gate before a little bit of
the (same) clk edge gets through.

It's at the end after all the counting is done and doesn't have any
effect... Still (according to H&H) it's bad form.

Here it is..
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0

Ch1 is the clock Ch2 is the output pulse (negative true)
C3 is the signal after the Nand gate that goes to the counters.

Here's a pic where I'm clocking at 1 MHz... so you can see clk and
glitch. https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0

Hey, Maybe if instead of gating the clock I can just disable the
counter...

Have I said lately how much I like talking to you guys... even when
you're silent you still give me ideas :^)

OK. So it's not the flip-flop that's causing the glitch -- it's trying
to use the output of the flip-flop to turn a clock on and off that's
causing the glitch. That makes sense.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

 

[John Larkin]

On Tue, 19 Jan 2016 10:23:19 -0800 (PST), George Herold
<gherold@teachspin.com> wrote:

As part of reintroducing myself to digital electronics,
I've been reading chapter 10 of AoE3. My question regards the footnote
(60) on page 738. Fig 10.73 shows how a rising edge D-FF can make a glitch.
Putting an inverter in the clk line might make a glitch at the leading edge..
(if the D-flip is faster than the inverter.) So the rather obvious answer
is to stick the inverter before the clock input of the D-flip.. giving
two propagation delays in that section.... Is that the "right" answer?

Tia
George H.

There are places where you can get fired, if not beat up and left for
dead, for gating a clock line.

We've been having a horrible problem with one product. Turns out that
one input to a finite state machine is asynchronous level GO. The
state machine idles in state 0 and should proceed, on the next clock,
to state 1 when that async input goes high. Sometimes, rarely, it
hangs in state 0 for millions of clocks and ignores the GO input.
There is absolutely no explanation for that; the FPGA compiler did
something clever, optimized the logic, to make that happen.


--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[John Larkin]

On Wed, 20 Jan 2016 12:01:40 -0800 (PST), George Herold
<gherold@teachspin.com> wrote:

On Wednesday, January 20, 2016 at 2:59:39 PM UTC-5, George Herold wrote:
On Tuesday, January 19, 2016 at 4:23:33 PM UTC-5, Tim Wescott wrote:
On Tue, 19 Jan 2016 10:23:19 -0800, George Herold wrote:

As part of reintroducing myself to digital electronics,
I've been reading chapter 10 of AoE3. My question regards the footnote
(60) on page 738. Fig 10.73 shows how a rising edge D-FF can make a
glitch. Putting an inverter in the clk line might make a glitch at the
leading edge..
(if the D-flip is faster than the inverter.) So the rather obvious
answer is to stick the inverter before the clock input of the D-flip..
giving two propagation delays in that section.... Is that the "right"
answer?

Tia George H.

Post an ASCII-art schematic? I don't think I have revision 3.

--
www.wescottdesign.com

No third edition? Treat yourself and spend the money.
Here's a picture from Aoe3
https://www.dropbox.com/s/66qxydq710bjjgg/pg738.JPG?dl=0

I've got a similar little glitch in my circuit. A D-flip turns off with the rising
edge of the clock pulse, that goes to a Nand gate, but doesn't get there in time to
turn off the gate before a little bit of the (same) clk edge gets through.

It's at the end after all the counting is done and doesn't have any effect...
Still (according to H&H) it's bad form.

Here it is..
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0

Ch1 is the clock
Ch2 is the output pulse (negative true)
C3 is the signal after the Nand gate that goes to the counters.

Here's a pic where I'm clocking at 1 MHz... so you can see clk and glitch.
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0
dang wrong pic again... sorry,
https://www.dropbox.com/s/frz91exmlbvwluf/TEK0001.BMP?dl=0
better.

Hey, Maybe if instead of gating the clock I can just disable the counter...

Have I said lately how much I like talking to you guys... even when you're silent
you still give me ideas :^)

Cheers,
George H.

The True Gospel of synchronous logic requires that one master clock go
the the clock inputs of a lot of d-flops, and nowhere else.

TI once had a huge project called ASC, the Advanced Scientific
Computer. Designers were required to strap the /preset and /clear of
all flipflops to Vcc; they couldn't even be used for powerup reset.

The project was a failure, but it did result in a truly superior
technique for shooting rubber bands at the butts of admins. Several
marriages ensued.


--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[George Herold]

On Thursday, January 21, 2016 at 11:19:35 PM UTC-5, John Larkin wrote:

On Tue, 19 Jan 2016 10:23:19 -0800 (PST), George Herold
gherold@teachspin.com> wrote:

As part of reintroducing myself to digital electronics,
I've been reading chapter 10 of AoE3. My question regards the footnote
(60) on page 738. Fig 10.73 shows how a rising edge D-FF can make a glitch.
Putting an inverter in the clk line might make a glitch at the leading edge..
(if the D-flip is faster than the inverter.) So the rather obvious answer
is to stick the inverter before the clock input of the D-flip.. giving
two propagation delays in that section.... Is that the "right" answer?

Tia
George H.

There are places where you can get fired, if not beat up and left for
dead, for gating a clock line.

Grin.. I guess I'm not likely to get a job there then.
It is in AoE3.....

We've been having a horrible problem with one product. Turns out that
one input to a finite state machine is asynchronous level GO. The
state machine idles in state 0 and should proceed, on the next clock,
to state 1 when that async input goes high. Sometimes, rarely, it
hangs in state 0 for millions of clocks and ignores the GO input.
There is absolutely no explanation for that; the FPGA compiler did
something clever, optimized the logic, to make that happen.

I've been reading the digital chapters of AoE3, it seems like digital design
has now turned into programming. Is there any way to see what the optimized gates
configuration looks like?

George H.

--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[George Herold]

On Thursday, January 21, 2016 at 11:27:25 PM UTC-5, John Larkin wrote:

On Wed, 20 Jan 2016 12:01:40 -0800 (PST), George Herold
gherold@teachspin.com> wrote:

On Wednesday, January 20, 2016 at 2:59:39 PM UTC-5, George Herold wrote:
On Tuesday, January 19, 2016 at 4:23:33 PM UTC-5, Tim Wescott wrote:
On Tue, 19 Jan 2016 10:23:19 -0800, George Herold wrote:

As part of reintroducing myself to digital electronics,
I've been reading chapter 10 of AoE3. My question regards the footnote
(60) on page 738. Fig 10.73 shows how a rising edge D-FF can make a
glitch. Putting an inverter in the clk line might make a glitch at the
leading edge..
(if the D-flip is faster than the inverter.) So the rather obvious
answer is to stick the inverter before the clock input of the D-flip..
giving two propagation delays in that section.... Is that the "right"
answer?

Tia George H.

Post an ASCII-art schematic? I don't think I have revision 3.

--
www.wescottdesign.com

No third edition? Treat yourself and spend the money.
Here's a picture from Aoe3
https://www.dropbox.com/s/66qxydq710bjjgg/pg738.JPG?dl=0

I've got a similar little glitch in my circuit. A D-flip turns off with the rising
edge of the clock pulse, that goes to a Nand gate, but doesn't get there in time to
turn off the gate before a little bit of the (same) clk edge gets through.

It's at the end after all the counting is done and doesn't have any effect...
Still (according to H&H) it's bad form.

Here it is..
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0

Ch1 is the clock
Ch2 is the output pulse (negative true)
C3 is the signal after the Nand gate that goes to the counters.

Here's a pic where I'm clocking at 1 MHz... so you can see clk and glitch.
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0
dang wrong pic again... sorry,
https://www.dropbox.com/s/frz91exmlbvwluf/TEK0001.BMP?dl=0
better.

Hey, Maybe if instead of gating the clock I can just disable the counter...

Have I said lately how much I like talking to you guys... even when you're silent
you still give me ideas :^)

Cheers,
George H.

The True Gospel of synchronous logic requires that one master clock go
the the clock inputs of a lot of d-flops, and nowhere else.

Yeah it seems with a clk->D-flip->Gate as in AoE, that you either have to
get a glitch.. delay in the D-flip, or delay the clock to the D-flip...
which means it's a "little less" synchronous.


My current config has the clock going to the counters..
(I assume there are D-flips inside there somewhere.) And a single '74
that sync's the "start" signal with the clock. It looks OK to me now,
but it took me a few hacks to get there..

George H.

TI once had a huge project called ASC, the Advanced Scientific
Computer. Designers were required to strap the /preset and /clear of
all flipflops to Vcc; they couldn't even be used for powerup reset.

The project was a failure, but it did result in a truly superior
technique for shooting rubber bands at the butts of admins. Several
marriages ensued.


--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[John Larkin]

On Fri, 22 Jan 2016 06:03:17 -0800 (PST), George Herold
<gherold@teachspin.com> wrote:

On Thursday, January 21, 2016 at 11:19:35 PM UTC-5, John Larkin wrote:
On Tue, 19 Jan 2016 10:23:19 -0800 (PST), George Herold
gherold@teachspin.com> wrote:

As part of reintroducing myself to digital electronics,
I've been reading chapter 10 of AoE3. My question regards the footnote
(60) on page 738. Fig 10.73 shows how a rising edge D-FF can make a glitch.
Putting an inverter in the clk line might make a glitch at the leading edge..
(if the D-flip is faster than the inverter.) So the rather obvious answer
is to stick the inverter before the clock input of the D-flip.. giving
two propagation delays in that section.... Is that the "right" answer?

Tia
George H.

There are places where you can get fired, if not beat up and left for
dead, for gating a clock line.

Grin.. I guess I'm not likely to get a job there then.
It is in AoE3.....

We've been having a horrible problem with one product. Turns out that
one input to a finite state machine is asynchronous level GO. The
state machine idles in state 0 and should proceed, on the next clock,
to state 1 when that async input goes high. Sometimes, rarely, it
hangs in state 0 for millions of clocks and ignores the GO input.
There is absolutely no explanation for that; the FPGA compiler did
something clever, optimized the logic, to make that happen.

I've been reading the digital chapters of AoE3, it seems like digital design
has now turned into programming. Is there any way to see what the optimized gates
configuration looks like?

Probably, but it would be difficult.

Most logic design is now language-based, and fairly abstract, and the
compilers estimate your intent and design the logic. If I'd done that
state machine at the gate/flop level, it would have worked, with only
a predictably tolerable metastability hazard.

The serious difference between C and Verilog is that classic
programming is procedural and HDLs are hardware descriptive. A 'for'
loop in C executes N times, whereas a for loop in VHDL generates
hardware N times.

Some people love the layered abstraction of HDLs. I don't. But
properly done, it tends to work.


--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[Phil Hobbs]

On 01/21/2016 11:27 PM, John Larkin wrote:

On Wed, 20 Jan 2016 12:01:40 -0800 (PST), George Herold
gherold@teachspin.com> wrote:

On Wednesday, January 20, 2016 at 2:59:39 PM UTC-5, George Herold wrote:
On Tuesday, January 19, 2016 at 4:23:33 PM UTC-5, Tim Wescott wrote:
On Tue, 19 Jan 2016 10:23:19 -0800, George Herold wrote:

As part of reintroducing myself to digital electronics,
I've been reading chapter 10 of AoE3. My question regards the footnote
(60) on page 738. Fig 10.73 shows how a rising edge D-FF can make a
glitch. Putting an inverter in the clk line might make a glitch at the
leading edge..
(if the D-flip is faster than the inverter.) So the rather obvious
answer is to stick the inverter before the clock input of the D-flip..
giving two propagation delays in that section.... Is that the "right"
answer?

Tia George H.

Post an ASCII-art schematic? I don't think I have revision 3.

--
www.wescottdesign.com

No third edition? Treat yourself and spend the money.
Here's a picture from Aoe3
https://www.dropbox.com/s/66qxydq710bjjgg/pg738.JPG?dl=0

I've got a similar little glitch in my circuit. A D-flip turns off with the rising
edge of the clock pulse, that goes to a Nand gate, but doesn't get there in time to
turn off the gate before a little bit of the (same) clk edge gets through.

It's at the end after all the counting is done and doesn't have any effect...
Still (according to H&H) it's bad form.

Here it is..
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0

Ch1 is the clock
Ch2 is the output pulse (negative true)
C3 is the signal after the Nand gate that goes to the counters.

Here's a pic where I'm clocking at 1 MHz... so you can see clk and glitch.
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0
dang wrong pic again... sorry,
https://www.dropbox.com/s/frz91exmlbvwluf/TEK0001.BMP?dl=0
better.

Hey, Maybe if instead of gating the clock I can just disable the counter...

Have I said lately how much I like talking to you guys... even when you're silent
you still give me ideas :^)

Cheers,
George H.

The True Gospel of synchronous logic requires that one master clock go
the the clock inputs of a lot of d-flops, and nowhere else.

TI once had a huge project called ASC, the Advanced Scientific
Computer. Designers were required to strap the /preset and /clear of
all flipflops to Vcc; they couldn't even be used for powerup reset.

The project was a failure, but it did result in a truly superior
technique for shooting rubber bands at the butts of admins. Several
marriages ensued.

Since I'm pretty sure you never worked at TI, and your lovely wife is a
speech pathologist, I'd love to hear how you heard about this. Could be
useful for some of the younger younger generation.

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[John Larkin]

On Sat, 23 Jan 2016 17:12:52 -0500, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 01/21/2016 11:27 PM, John Larkin wrote:
On Wed, 20 Jan 2016 12:01:40 -0800 (PST), George Herold
gherold@teachspin.com> wrote:

On Wednesday, January 20, 2016 at 2:59:39 PM UTC-5, George Herold wrote:
On Tuesday, January 19, 2016 at 4:23:33 PM UTC-5, Tim Wescott wrote:
On Tue, 19 Jan 2016 10:23:19 -0800, George Herold wrote:

As part of reintroducing myself to digital electronics,
I've been reading chapter 10 of AoE3. My question regards the footnote
(60) on page 738. Fig 10.73 shows how a rising edge D-FF can make a
glitch. Putting an inverter in the clk line might make a glitch at the
leading edge..
(if the D-flip is faster than the inverter.) So the rather obvious
answer is to stick the inverter before the clock input of the D-flip..
giving two propagation delays in that section.... Is that the "right"
answer?

Tia George H.

Post an ASCII-art schematic? I don't think I have revision 3.

--
www.wescottdesign.com

No third edition? Treat yourself and spend the money.
Here's a picture from Aoe3
https://www.dropbox.com/s/66qxydq710bjjgg/pg738.JPG?dl=0

I've got a similar little glitch in my circuit. A D-flip turns off with the rising
edge of the clock pulse, that goes to a Nand gate, but doesn't get there in time to
turn off the gate before a little bit of the (same) clk edge gets through.

It's at the end after all the counting is done and doesn't have any effect...
Still (according to H&H) it's bad form.

Here it is..
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0

Ch1 is the clock
Ch2 is the output pulse (negative true)
C3 is the signal after the Nand gate that goes to the counters.

Here's a pic where I'm clocking at 1 MHz... so you can see clk and glitch.
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0
dang wrong pic again... sorry,
https://www.dropbox.com/s/frz91exmlbvwluf/TEK0001.BMP?dl=0
better.

Hey, Maybe if instead of gating the clock I can just disable the counter...

Have I said lately how much I like talking to you guys... even when you're silent
you still give me ideas :^)

Cheers,
George H.

The True Gospel of synchronous logic requires that one master clock go
the the clock inputs of a lot of d-flops, and nowhere else.

TI once had a huge project called ASC, the Advanced Scientific
Computer. Designers were required to strap the /preset and /clear of
all flipflops to Vcc; they couldn't even be used for powerup reset.

The project was a failure, but it did result in a truly superior
technique for shooting rubber bands at the butts of admins. Several
marriages ensued.

Since I'm pretty sure you never worked at TI, and your lovely wife is a
speech pathologist, I'd love to hear how you heard about this. Could be
useful for some of the younger younger generation.

A veteran of the project worked for me at TANO in New Orleans.

I could show you the rubber band thing in a few seconds. I haven't
already?

In words,

Place left hand with thumb pointing at your face, index finger
pointing away.

Stretch a fat rubber band between those fingers.

Place your right index finger on the stretched band, inside-right
side, near thumb, and hook it and pull forward, transferring the
tension from left index to right index. You now have a band with a lot
more tension on one side than the other, between left thumb and right
index.

Stretch hard, aim at admin, fire.

The band spins and doesn't tumble. It goes like a bullet. Whack.


--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[Phil Hobbs]

On 01/23/2016 11:36 PM, John Larkin wrote:

On Sat, 23 Jan 2016 17:12:52 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 01/21/2016 11:27 PM, John Larkin wrote:
On Wed, 20 Jan 2016 12:01:40 -0800 (PST), George Herold
gherold@teachspin.com> wrote:

On Wednesday, January 20, 2016 at 2:59:39 PM UTC-5, George Herold wrote:
On Tuesday, January 19, 2016 at 4:23:33 PM UTC-5, Tim Wescott wrote:
On Tue, 19 Jan 2016 10:23:19 -0800, George Herold wrote:

As part of reintroducing myself to digital electronics,
I've been reading chapter 10 of AoE3. My question regards the footnote
(60) on page 738. Fig 10.73 shows how a rising edge D-FF can make a
glitch. Putting an inverter in the clk line might make a glitch at the
leading edge..
(if the D-flip is faster than the inverter.) So the rather obvious
answer is to stick the inverter before the clock input of the D-flip..
giving two propagation delays in that section.... Is that the "right"
answer?

Tia George H.

Post an ASCII-art schematic? I don't think I have revision 3.

--
www.wescottdesign.com

No third edition? Treat yourself and spend the money.
Here's a picture from Aoe3
https://www.dropbox.com/s/66qxydq710bjjgg/pg738.JPG?dl=0

I've got a similar little glitch in my circuit. A D-flip turns off with the rising
edge of the clock pulse, that goes to a Nand gate, but doesn't get there in time to
turn off the gate before a little bit of the (same) clk edge gets through.

It's at the end after all the counting is done and doesn't have any effect...
Still (according to H&H) it's bad form.

Here it is..
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0

Ch1 is the clock
Ch2 is the output pulse (negative true)
C3 is the signal after the Nand gate that goes to the counters.

Here's a pic where I'm clocking at 1 MHz... so you can see clk and glitch.
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0
dang wrong pic again... sorry,
https://www.dropbox.com/s/frz91exmlbvwluf/TEK0001.BMP?dl=0
better.

Hey, Maybe if instead of gating the clock I can just disable the counter...

Have I said lately how much I like talking to you guys... even when you're silent
you still give me ideas :^)

Cheers,
George H.

The True Gospel of synchronous logic requires that one master clock go
the the clock inputs of a lot of d-flops, and nowhere else.

TI once had a huge project called ASC, the Advanced Scientific
Computer. Designers were required to strap the /preset and /clear of
all flipflops to Vcc; they couldn't even be used for powerup reset.

The project was a failure, but it did result in a truly superior
technique for shooting rubber bands at the butts of admins. Several
marriages ensued.

Since I'm pretty sure you never worked at TI, and your lovely wife is a
speech pathologist, I'd love to hear how you heard about this. Could be
useful for some of the younger younger generation.

A veteran of the project worked for me at TANO in New Orleans.

I could show you the rubber band thing in a few seconds. I haven't
already?

In words,

Place left hand with thumb pointing at your face, index finger
pointing away.

Stretch a fat rubber band between those fingers.

Place your right index finger on the stretched band, inside-right
side, near thumb, and hook it and pull forward, transferring the
tension from left index to right index. You now have a band with a lot
more tension on one side than the other, between left thumb and right
index.

Stretch hard, aim at admin, fire.

The band spins and doesn't tumble. It goes like a bullet. Whack.

Engineers' courtship rituals are obviously a neglected field of
ethnology. We physicists wave our arms and make funny noises. Works
every time. (At least, I'm one-for-one, as of 32 years ago.)

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Jim Thompson]

On Sun, 24 Jan 2016 16:06:43 -0500, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

[snip]

Engineers' courtship rituals are obviously a neglected field of
ethnology. We physicists wave our arms and make funny noises. Works
every time. (At least, I'm one-for-one, as of 32 years ago.)

Cheers

Phil Hobbs

We engineers do the funny noises, but we don't wave our arms, we wave
something else ;-)

56 years as of March 1 !!

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Tim Wescott]

On Wed, 20 Jan 2016 18:05:06 -0800, George Herold wrote:

On Wednesday, January 20, 2016 at 5:38:45 PM UTC-5, Tim Wescott wrote:
On Wed, 20 Jan 2016 11:59:36 -0800, George Herold wrote:

On Tuesday, January 19, 2016 at 4:23:33 PM UTC-5, Tim Wescott wrote:
On Tue, 19 Jan 2016 10:23:19 -0800, George Herold wrote:

As part of reintroducing myself to digital electronics,
I've been reading chapter 10 of AoE3. My question regards the
footnote (60) on page 738. Fig 10.73 shows how a rising edge D-FF
can make a glitch. Putting an inverter in the clk line might make
a glitch at the leading edge..
(if the D-flip is faster than the inverter.) So the rather
obvious answer is to stick the inverter before the clock input of
the D-flip.. giving two propagation delays in that section.... Is
that the "right" answer?

Tia George H.

Post an ASCII-art schematic? I don't think I have revision 3.

--
www.wescottdesign.com

No third edition? Treat yourself and spend the money.
Here's a picture from Aoe3
https://www.dropbox.com/s/66qxydq710bjjgg/pg738.JPG?dl=0

I've got a similar little glitch in my circuit. A D-flip turns off
with the rising edge of the clock pulse, that goes to a Nand gate,
but doesn't get there in time to turn off the gate before a little
bit of the (same) clk edge gets through.

It's at the end after all the counting is done and doesn't have any
effect... Still (according to H&H) it's bad form.

Here it is..
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0

Ch1 is the clock Ch2 is the output pulse (negative true)
C3 is the signal after the Nand gate that goes to the counters.

Here's a pic where I'm clocking at 1 MHz... so you can see clk and
glitch. https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0

Hey, Maybe if instead of gating the clock I can just disable the
counter...

Have I said lately how much I like talking to you guys... even when
you're silent you still give me ideas :^)

OK. So it's not the flip-flop that's causing the glitch -- it's trying
to use the output of the flip-flop to turn a clock on and off that's
causing the glitch. That makes sense.

--

Tim Wescott Wescott Design Services http://www.wescottdesign.com

It's OK I got rid of the glitch by getting rid of the AND gate (nand in
my case)
I use the D flip to enable the counter skipping the redundant AND gate.
The counter down counts and when it gets to the end, it turns off a S/R
which is feed to the D input of the D-flip. It seems like a clean loop
now.
I'm not very good at digital... I don't do it often enough.

I wanted to say, I didn't want to do this project.
But once I mentioned it, I felt obligated to finish it up..
(a good thing.)
Hey, there's got to be a pcb soon. I had this crazy idea of laying out
the IC's so that I could stick in DIP's and later smd's onto the same
board spin.
(Assuming the pin-out matches up..
I better check..
later

George H.

I just use SMD and build the board turn-around into my work schedule (or
go to a fast-turn house as needed). Then I modify boards as necessary
when I screw up.

Come to think of it, part of Friday's work was finding out that I'd used
a narrow SSOP package where I needed a wide. I ended up soldering the
chip at a 45 degree angle on one edge, then wiring up the other edge
where it was standing up in space. That's not going to be a production
mod, for some reason.

--
www.wescottdesign.com

 

[John Larkin]

On Sun, 24 Jan 2016 16:06:43 -0500, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 01/23/2016 11:36 PM, John Larkin wrote:
On Sat, 23 Jan 2016 17:12:52 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 01/21/2016 11:27 PM, John Larkin wrote:
On Wed, 20 Jan 2016 12:01:40 -0800 (PST), George Herold
gherold@teachspin.com> wrote:

On Wednesday, January 20, 2016 at 2:59:39 PM UTC-5, George Herold wrote:
On Tuesday, January 19, 2016 at 4:23:33 PM UTC-5, Tim Wescott wrote:
On Tue, 19 Jan 2016 10:23:19 -0800, George Herold wrote:

As part of reintroducing myself to digital electronics,
I've been reading chapter 10 of AoE3. My question regards the footnote
(60) on page 738. Fig 10.73 shows how a rising edge D-FF can make a
glitch. Putting an inverter in the clk line might make a glitch at the
leading edge..
(if the D-flip is faster than the inverter.) So the rather obvious
answer is to stick the inverter before the clock input of the D-flip..
giving two propagation delays in that section.... Is that the "right"
answer?

Tia George H.

Post an ASCII-art schematic? I don't think I have revision 3.

--
www.wescottdesign.com

No third edition? Treat yourself and spend the money.
Here's a picture from Aoe3
https://www.dropbox.com/s/66qxydq710bjjgg/pg738.JPG?dl=0

I've got a similar little glitch in my circuit. A D-flip turns off with the rising
edge of the clock pulse, that goes to a Nand gate, but doesn't get there in time to
turn off the gate before a little bit of the (same) clk edge gets through.

It's at the end after all the counting is done and doesn't have any effect...
Still (according to H&H) it's bad form.

Here it is..
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0

Ch1 is the clock
Ch2 is the output pulse (negative true)
C3 is the signal after the Nand gate that goes to the counters.

Here's a pic where I'm clocking at 1 MHz... so you can see clk and glitch.
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0
dang wrong pic again... sorry,
https://www.dropbox.com/s/frz91exmlbvwluf/TEK0001.BMP?dl=0
better.

Hey, Maybe if instead of gating the clock I can just disable the counter...

Have I said lately how much I like talking to you guys... even when you're silent
you still give me ideas :^)

Cheers,
George H.

The True Gospel of synchronous logic requires that one master clock go
the the clock inputs of a lot of d-flops, and nowhere else.

TI once had a huge project called ASC, the Advanced Scientific
Computer. Designers were required to strap the /preset and /clear of
all flipflops to Vcc; they couldn't even be used for powerup reset.

The project was a failure, but it did result in a truly superior
technique for shooting rubber bands at the butts of admins. Several
marriages ensued.

Since I'm pretty sure you never worked at TI, and your lovely wife is a
speech pathologist, I'd love to hear how you heard about this. Could be
useful for some of the younger younger generation.

A veteran of the project worked for me at TANO in New Orleans.

I could show you the rubber band thing in a few seconds. I haven't
already?

In words,

Place left hand with thumb pointing at your face, index finger
pointing away.

Stretch a fat rubber band between those fingers.

Place your right index finger on the stretched band, inside-right
side, near thumb, and hook it and pull forward, transferring the
tension from left index to right index. You now have a band with a lot
more tension on one side than the other, between left thumb and right
index.

Stretch hard, aim at admin, fire.

The band spins and doesn't tumble. It goes like a bullet. Whack.

Engineers' courtship rituals are obviously a neglected field of
ethnology. We physicists wave our arms and make funny noises. Works
every time. (At least, I'm one-for-one, as of 32 years ago.)

Cheers

Phil Hobbs

"Women have no use for engineers except to marry them."

There is a certain type of woman who likes engineers, and it is a
pretty good type of woman.


--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[George Herold]

On Sunday, January 24, 2016 at 4:06:59 PM UTC-5, Phil Hobbs wrote:

On 01/23/2016 11:36 PM, John Larkin wrote:
On Sat, 23 Jan 2016 17:12:52 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 01/21/2016 11:27 PM, John Larkin wrote:
On Wed, 20 Jan 2016 12:01:40 -0800 (PST), George Herold
gherold@teachspin.com> wrote:

On Wednesday, January 20, 2016 at 2:59:39 PM UTC-5, George Herold wrote:
On Tuesday, January 19, 2016 at 4:23:33 PM UTC-5, Tim Wescott wrote:
On Tue, 19 Jan 2016 10:23:19 -0800, George Herold wrote:

As part of reintroducing myself to digital electronics,
I've been reading chapter 10 of AoE3. My question regards the footnote
(60) on page 738. Fig 10.73 shows how a rising edge D-FF can make a
glitch. Putting an inverter in the clk line might make a glitch at the
leading edge..
(if the D-flip is faster than the inverter.) So the rather obvious
answer is to stick the inverter before the clock input of the D-flip..
giving two propagation delays in that section.... Is that the "right"
answer?

Tia George H.

Post an ASCII-art schematic? I don't think I have revision 3.

--
www.wescottdesign.com

No third edition? Treat yourself and spend the money.
Here's a picture from Aoe3
https://www.dropbox.com/s/66qxydq710bjjgg/pg738.JPG?dl=0

I've got a similar little glitch in my circuit. A D-flip turns off with the rising
edge of the clock pulse, that goes to a Nand gate, but doesn't get there in time to
turn off the gate before a little bit of the (same) clk edge gets through.

It's at the end after all the counting is done and doesn't have any effect...
Still (according to H&H) it's bad form.

Here it is..
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0

Ch1 is the clock
Ch2 is the output pulse (negative true)
C3 is the signal after the Nand gate that goes to the counters.

Here's a pic where I'm clocking at 1 MHz... so you can see clk and glitch.
https://www.dropbox.com/s/vrx7w8aljmofik6/TEK0000.BMP?dl=0
dang wrong pic again... sorry,
https://www.dropbox.com/s/frz91exmlbvwluf/TEK0001.BMP?dl=0
better.

Hey, Maybe if instead of gating the clock I can just disable the counter...

Have I said lately how much I like talking to you guys... even when you're silent
you still give me ideas :^)

Cheers,
George H.

The True Gospel of synchronous logic requires that one master clock go
the the clock inputs of a lot of d-flops, and nowhere else.

TI once had a huge project called ASC, the Advanced Scientific
Computer. Designers were required to strap the /preset and /clear of
all flipflops to Vcc; they couldn't even be used for powerup reset.

The project was a failure, but it did result in a truly superior
technique for shooting rubber bands at the butts of admins. Several
marriages ensued.

Since I'm pretty sure you never worked at TI, and your lovely wife is a
speech pathologist, I'd love to hear how you heard about this. Could be
useful for some of the younger younger generation.

A veteran of the project worked for me at TANO in New Orleans.

I could show you the rubber band thing in a few seconds. I haven't
already?

In words,

Place left hand with thumb pointing at your face, index finger
pointing away.

Stretch a fat rubber band between those fingers.

Place your right index finger on the stretched band, inside-right
side, near thumb, and hook it and pull forward, transferring the
tension from left index to right index. You now have a band with a lot
more tension on one side than the other, between left thumb and right
index.

Stretch hard, aim at admin, fire.

The band spins and doesn't tumble. It goes like a bullet. Whack.

Engineers' courtship rituals are obviously a neglected field of
ethnology. We physicists wave our arms and make funny noises. Works
every time. (At least, I'm one-for-one, as of 32 years ago.)

Yes I thought you were asking how rubber bands lead to matrimony.
Are these female coders snipping at the little derrieres of the male
admin's. Or males taking aim at some female mega-fhany... and how
does that lead to courtship? These are important questions
for young geeks.

George H.

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net