Anyone know how to interact with the simulator console w/ ve

J

JT

Guest
During the simulation I want to query the user for interactive
test parameters. I really don't want to have to go through the PLI
and I was hoping that the new file IO features of verilog 2001 would
do the job. I'm using a Modelsim PE simulator and I tried the following
code snippet however it didn't work as expected.

The call to getc (also tried getchar()) always returns 0x00 so something is
wrong here.

Anyone have any thoughts on doing console IO during a simulation run?


integer i_char;
reg done;

initial
begin
..
..
..
$display ("Module %m: At %d: Enter a character", $time);
done = 0;
while (!done)
begin
i_char = $getc();
if (i_char != 8'h00)
done = 1;
end
$display ("Module %m: At %d: The character was: %h", $time, i_char);
 
Hello,

JT wrote:
Anyone have any thoughts on doing console IO during a simulation run?
It is not that interactive, but the following fits my needs perfectly:
There is a shell script for every simulation file. The script asks for
parameters before starting the simulation:

OFFSETREG=256
until [ $OFFSETREG -ge 0 -a $OFFSETREG -le 255 ]; do
echo -n " Offset register: "; read OFFSETREG
done

the value is then passed to verilog-XL as a command line argument:
+define+OFFSET=$OFFSETREG

and can now be used within the simulation:
initial begin
Offset = `SIMOFFSETREG;
end

As I said, it's not really interactive - parameters are chosen before
simulation starts - but it offers more flexibility than editing the
simulation file for every new set of parameters.


HTH,

Uwe
 
jthibeault@yahoo.com (JT) wrote in message news:<ea38511d.0405120649.2468adfb@posting.google.com>...
During the simulation I want to query the user for interactive
test parameters. I really don't want to have to go through the PLI
and I was hoping that the new file IO features of verilog 2001 would
do the job. I'm using a Modelsim PE simulator and I tried the following
code snippet however it didn't work as expected.

The call to getc (also tried getchar()) always returns 0x00 so something is
wrong here.
Verilog-2001 did not define a $getc or $getchar. I am surprised that your
simulator did not give you an error when you used an undefined system
function. Perhaps your simulator has nonstandard system functions with
these names.

Verilog-2001 did define a $fgetc (and $fgets and $fscanf). It also specified
that a file descriptor value of 32'h8000_0000 would represent the pre-opened
file descriptor for standard input. You may be able to get your desired
functionality by calling these system functions with the special file
descriptor for standard input.

This assumes that your simulator implements these system functions and the
special file descriptors, and treats the simulator console as standard input.
Note that if the simulator brings up a separate window for the console, its
input may not be the same as standard input for the simulator executable.
Also note that standard input is generally not "raw" input, which means that
you won't see any input until the user finishes a line and hits return. You
may also see interference between the simulator trying to read command input
from the console and the Verilog program trying to read from it.
 

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