any simple flow from VHDL to technology ?

[N. Hervé]

Hi everyone !

I'm quite lost in the forest of all cadence softwares ...

I want to use a top-down methology, from behavioural VHDL to a given
technology (layout)
for digital circuits.
So first, I think I need some High Level Compiler to obtain RTL-VHDL,
and then a RTL compiler to map the choosen technology.
After that, I will do some timing and power analysis to identify the
bottlenecks and
then refine the design in instanciating custom design blocks.

Can someone point at what I should first have a look for my need.

Thank you.


P.S.: I prefer command line tools to clickmachine (GUI)

 

[N. Hervé]

On 19 avr, 12:15, N. Hervé <nicolas.he...@gmail.com> wrote:

Hi everyone !

I'm quite lost in the forest of all cadence softwares ...

I want to use a top-down methology, from behavioural VHDL to a given
technology (layout)
for digital circuits.
So first, I think I need some High Level Compiler to obtain RTL-VHDL,
and then a RTL compiler to map the choosen technology.
After that, I will do some timing and power analysis to identify the
bottlenecks and
then refine the design in instanciating custom design blocks.

Can someone point at what I should first have a look for my need.

Thank you.

P.S.: I prefer command line tools to clickmachine (GUI)

Please ...

 

[Svenn Are Bjerkem]

On Apr 24, 7:12 pm, N. Hervé <nicolas.he...@gmail.com> wrote:

Please ...

I think you will have to ask Cadence sales for a little help, here.
Most digital designers frown upon Cadence tools for digital, and
specially upon Cadence and VHDL. (Cadence favors Verilog, the enemy of
VHDL, you know). I heard from a friend that Cadence is soooo keen on
pushing their tools into the digital domain. Your problem is that
sales at Cadence don't seem to mingle in comp.cad.cadence.

--
Svenn

 

[Andrew Beckett]

On 30 Apr 2007 04:56:29 -0700, Svenn Are Bjerkem <svenn.bjerkem@googlemail.com>
wrote:

On Apr 24, 7:12 pm, N. Hervé <nicolas.he...@gmail.com> wrote:

Please ...

I think you will have to ask Cadence sales for a little help, here.
Most digital designers frown upon Cadence tools for digital, and
specially upon Cadence and VHDL. (Cadence favors Verilog, the enemy of
VHDL, you know). I heard from a friend that Cadence is soooo keen on
pushing their tools into the digital domain. Your problem is that
sales at Cadence don't seem to mingle in comp.cad.cadence.

Well, Cadence's digital simulator, ncsim, supports VHDL, and always has done.
Prior to that Cadence had a VHDL-specific simulator, leapfrog.

From the synthesis point of view, Cadence has a tool "RTL Compiler" which will
equally well support VHDL. Prior to that there was BuildGates which also
supported VHDL.

At the implementation phase (Encounter), you need a connectivity netlist, and
for that it would be Verilog (Verilog is more commonly used for gate level
netlists than VHDL), but since Synthesis tools (RTL Compiler included) can read
VHDL and spit out Verilog, this shouldn't be a problem.

I don't think Cadence particularly favours Verilog over VHDL - support is fairly
good within the tools - the level of support of each tends to follow the size of
the user base of the two languages.

Cadence have supported digital tools for as long as Cadence has existed, so
pushing them into the digital domain is hardly a new idea ;-> After all, Verilog
itself came from Gateway (which became part of Cadence back in 1988 or there
abouts), and Cadence have always had digital implementation tools with a good
market share. I think your "most digital designers" is not that accurate...

(I didn't respond to the question earlier primarily because I've been busy and
I'm more of a Custom IC guy..., but wanted to respond to this slightly cynical
posting).

Regards,

Andrew.
--
Andrew Beckett
Principal European Technology Leader
Cadence Design Systems, UK.