any program can generate block diagrams?

[Aiken]

I provide RTL code and the program will generate block diagrams with
connection between blocks

Is it possible?

 

[Mike Treseler]

Aiken wrote:

I provide RTL code and the program will generate block diagrams with
connection between blocks

Is it possible?

Yes, see:
http://mysite.verizon.net/miketreseler/stack.pdf
I use the quartus RTL viewer which requires a license.

The ise webpack viewer is free, but not as pretty.
Emacs vhdl-mode speedbar is free, but uses text.
Everything else is expensive or fussy.

-- Mike Treseler

 

[Jeff Cunningham]

Aiken wrote:

I provide RTL code and the program will generate block diagrams with
connection between blocks

Is it possible?

Mentor used to have a product called Renoir that could do this.
Apparently the name has changed and searching for it leads here:

http://www.mentor.com/products/fpga/request?

I'm guessing its not cheap.

-Jeff

 

[Dave]

On Apr 23, 5:50 pm, Aiken <aikenp...@gmail.com> wrote:

I provide RTL code and the program will generate block diagrams with
connection between blocks

Is it possible?

Three free utilities might help: doxygen, VHdocL, and VHDLdoc.

Even though doxygen was originally made for software (C/C++/Java), it
does have a VHDL mode and I'm told they've made improvements to the
VHDL support.

I've played a bit with VHDLdoc and VHdocL. I'm not a fan of VHDLdoc -
too many restrictions on coding style for my liking. VHdocL is pretty
simple and might get you something like a block diagram quickly.

Hope this helps.

Dave

 

[HT-Lab]

"Jeff Cunningham" <jcc@sover.net> wrote in message
news:49f11357$0$2711$4d3efbfe@news.sover.net...

Aiken wrote:
I provide RTL code and the program will generate block diagrams with
connection between blocks

Is it possible?

Mentor used to have a product called Renoir that could do this. Apparently
the name has changed and searching for it leads here:

That name has changed probably close to 10 years ago

It is now called HDL Designer/Author and it is a great product (but as you
mentioned not cheap).

Hans
www.ht-lab.com

http://www.mentor.com/products/fpga/request?

I'm guessing its not cheap.

-Jeff

 

[Bert_Paris]

Last time I checked (quite a while ago), ease HDL was a pretty good
tool: http://www.hdlworks.com/products/ease/index.html
btw: AFAIK, you don't need the subscription version to use Quartus' RTL
Viewer, it's free, included in the Web Edition.

Bert

 

[Marcus Harnisch]

Aiken <aikenpang@gmail.com> writes:

I provide RTL code and the program will generate block diagrams with
connection between blocks

SpringSoft (formerly Novas) Verdi. Costs a bit, though. Best RTL debug
tool I have used so far.

Regards
Marcus
--
note that "property" can also be used as syntaxtic sugar to reference
a property, breaking the clean design of verilog; [...]

(seen on http://www.veripool.com/verilog-mode_news.html)

 

[Daniel Leu]

RTLvision from Concept Engineering (http://concept.de/rtl_index.html)
would be an other option.

Regards,
Daniel

 

[Petter Gustad]

Aiken <aikenpang@gmail.com> writes:

I provide RTL code and the program will generate block diagrams with
connection between blocks

If you have access to a Synopsys Design Compiler license you can do
this with the create_schematic and plot -output filename.ps commands,
but it might be more detailed that what you want depending upon which
blocks you set_dont_touch etc.

Petter
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