D
Daku
Guest
Could some Verilog guru please help me ? I have heard of the analog/
mixed signal extension to Verilog - is there any open-source tool
somewhere that supports this ? For example,
SystemC has a freely downloadable version of SystemC AMS and I was
wondering if there is
any similar package for Verilog. I have also
looked at the SMASH tool, but the free evaluation version is so
stripped down, that I doubt I would be able to do anything useful with
it.
Any hints/suggestions would be very valubale.
Thanks in advance for your help.
mixed signal extension to Verilog - is there any open-source tool
somewhere that supports this ? For example,
SystemC has a freely downloadable version of SystemC AMS and I was
wondering if there is
any similar package for Verilog. I have also
looked at the SMASH tool, but the free evaluation version is so
stripped down, that I doubt I would be able to do anything useful with
it.
Any hints/suggestions would be very valubale.
Thanks in advance for your help.