Any idea about jumpered ports

[parag_paul@hotmail.com]

Verilog VPI allows you to iterate on mulitple ports for a particular
signal.
Is it possible to have more than one port for a same signal.

Somewhere I remember they were mentioned as jumpered ports. Can
anybody help me to it

I am not asking about portInsts, rather ports

 

[Jonathan Bromley]

On Sun, 01 Jul 2007 04:10:37 -0700, "parag_paul@hotmail.com"
<parag_paul@hotmail.com> wrote:

Is it possible to have more than one port for a same signal.

Yes. You can also have more than one signal on the same
port...

Somewhere I remember they were mentioned as jumpered ports. Can
anybody help me to it

module jumper( .a(L), .b(L) );
inout L;
endmodule

It's wild, bizarre syntax. The module has two ports called
"a" and "b". Those port names live in a different namespace
than the rest of the module, so I can't give them port
direction (or any other attributes) within the module
itself, since code inside the module can't see the port
names at all. So I must decorate the internal net L with
the port direction. However, you *can* make it look sensible
by using Verilog-2001 port declarations - and you can then
ascribe any direction to jumpered ports:

module passthrough( input wire .a(L), output wire .b(L) );
wire L;
endmodule
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