any good book about verilog for vhdl user from given list

[v_enthu]

hi guys i came across few topics already on it.
i am using now HDL programming VHDL and verilog by Nazeih M. Botros. though verilog learning is quite easy.i am finding it difficult to understand any language construct its scope(where to mention what for its definition and declaration and what there synthesis result). recently i tried to write booth algorithm it shows correct from syntax point of view but while doing simulation it will not produce intended results.similiar i found while using task in nested form for parameterized ripple carry adder.
nutshell,i think i need a book which covers both simulation and synthesis points in detail.i have verilog and sytem verilog gotchas book but they are not for beginner.someone suggested me to use 1- Verilog HDL : A guide to digital design and synthesis and other 2- Advanced Digital Design with the Verilog HDL by M.D. Cilleti. or Verilog golden reference guide 2001 or Verilog HDL by Vivek Sagdeoany or any other
please suggest any affordable book
regards
v_enthu

 

[Ralf Hildebrandt]

Hi v_enthu!

i think i need a book ...
please suggest any affordable book

I like "HDL Chip Design" by Douglas J. Smith ISBN-10: 0965193438

It shows for all problems both VHDL and Verilog source codes. As a
drawback it is a little bit more a beginners book and quite expensive.
Maybe you can get one in a library.

I general: Translation from VHDL to Verilog should be not too
complicated for synthessizeable code, because in such code only
flipflips, latches, comb. logic and maybe tristates can exist. And for
these elements it is quite easy to write Verilog code that looks just
similar to VHDL code. I will give you an example of my coding style:

always@(negedge reset_n or posedge clk)
begin
if(reset_n==1'b0) begin
my_sig <= 1'b0;
end else /*if posedge clk*/ begin
my_sig <= my_input;
end //+if
end //+always

process(reset_n, clk)
begin
if (reset_n='0') then
my_sig <= '0';
elsif rising_edge(clk) then
my_sig <= my_input;
end if;
end process;

And for blocking and non-blocking signal assignments use the VHDL rules:
* All VHDL variables (which use ":=") should use "=" in Verilog.
* All VHDL signals (which use "<=") should use "<=" in Verilog.

Ralf

 

[Gabor]

Ralf Hildebrandt wrote:

Hi v_enthu!

i think i need a book ...
please suggest any affordable book

I like "HDL Chip Design" by Douglas J. Smith ISBN-10: 0965193438

It shows for all problems both VHDL and Verilog source codes. As a
drawback it is a little bit more a beginners book and quite expensive.
Maybe you can get one in a library.

I general: Translation from VHDL to Verilog should be not too
complicated for synthessizeable code, because in such code only
flipflips, latches, comb. logic and maybe tristates can exist. And for
these elements it is quite easy to write Verilog code that looks just
similar to VHDL code. I will give you an example of my coding style:

always@(negedge reset_n or posedge clk)
begin
if(reset_n==1'b0) begin
my_sig <= 1'b0;
end else /*if posedge clk*/ begin
my_sig <= my_input;
end //+if
end //+always

process(reset_n, clk)
begin
if (reset_n='0') then
my_sig <= '0';
elsif rising_edge(clk) then
my_sig <= my_input;
end if;
end process;

And for blocking and non-blocking signal assignments use the VHDL rules:
* All VHDL variables (which use ":=") should use "=" in Verilog.
* All VHDL signals (which use "<=") should use "<=" in Verilog.

Ralf

I'd go a bit further with the variable "=" (blocking) and signal

(non-blocking) "<=" assignments.

1) The above statement implies a clocked process. Combinatorial
processes in Verilog should always use blocking "=" assignments.
Assignments outside of a process need to use the "assign" form
in Verilog:

VHDL:
foo <= bar;
Verilog:
assign foo = bar; // Using "<=" here will generate a syntax error

2) When using the equivalent of "variables" in verilog, I would
recommend declaring them locally to avoid use outside the process.
Otherwise you risk race conditions in simulation leading to
unpredictable differences between simulation and hardware.

always @ (posedge clk or negedge reset_n)
begin : named_proc
integer some_variable
reg [3:0] some_other_variable
if (!reset_n)
begin
// asynch reset terms go here
// even though it wouldn't seem to matter
// use blocking assignments for variables here, too
// synthesis will barf if you use both assignment types
// on the same variable
some_variable = 0;
some_other_variable = 4'd55; // Gotcha! 55 doesn't fit in 4 bits,
// but no warning or error!
my_sig <= 0; // Unsized constants are 32 bits, but don't need to
// match the variable's size, so this is legal
end
else
begin
// clocked terms go here
end
end

Note that you need a named process to include local declarations
within the process in Verilog. The process name will show up in
the netlist hierarchy for the local variables.

Obviously there are a lot more differences between the languages,
and it would be good to get a primer on how Verilog is simulated
to understand for example why you need to use edge sensitivity
for an asynchronous reset, when in hardware this would be a
level-sensitive input.

If you use Xilinx products, you can look at the language templates
for common sythesis constructs and see how they're done in both
languages as a guide to conversion for synthesis.

I haven't use VHDL for simulation at all, but I'm sure that's
where you'll need more help if you don't want to keep your
test benches in VHDL for your synthesizable Verilog projects.
Luckily it seems that most Verilog books spend most of their
pages on simulation constructs (and also unfortunately if
you were hoping to quickly get up to speed on Verilog for
synthesis).

-- Gabor