J
Jonathan Bromley
Guest
hi folks,
I've encountered what I believe is a bug in Icarus Verilog
(I'm using the 0.9.2 Windows binary). The Sourceforge
bug tracker claims that a similar bug was present in
version 0.8 and fixed in version 0.9, but I can't find
any other bug report that looks like it.
Before I slug through the usual process of distilling a
testcase, trawling the bug tracker thoroughly and filing
a bug report... has anyone else met this?
I'm trying to force an 8-bit vector net. If
I execute the force statement at time zero, it works.
If I execute it in the place I want it, after about
1ms of simulation time, it appears to have no effect.
Thanks for any comments
--
Jonathan Bromley
I've encountered what I believe is a bug in Icarus Verilog
(I'm using the 0.9.2 Windows binary). The Sourceforge
bug tracker claims that a similar bug was present in
version 0.8 and fixed in version 0.9, but I can't find
any other bug report that looks like it.
Before I slug through the usual process of distilling a
testcase, trawling the bug tracker thoroughly and filing
a bug report... has anyone else met this?
I'm trying to force an 8-bit vector net. If
I execute the force statement at time zero, it works.
If I execute it in the place I want it, after about
1ms of simulation time, it appears to have no effect.
Thanks for any comments
--
Jonathan Bromley