G
G
Guest
Thanks to all who have answered and helped me so far...I have looked at
this code over and over and for some reason, I don't see it...it is
supposed to create a 60 Hz signal? Am I missing something? A 60 Hz's
period is half a period of a 30 Hz signal...I don't see the code below
doing that...
It is used to supply a signal(to another module) that changes every 17
ms to XOR with the common bias and encoded seven segment data for
correct operation with an LCD....
// module: div_500K.v
// This module divides the incoming clock(30 Hz) by 2^19 and outputs
the
// 19th bit of the counter as a 60 Hz clock, clk_60.
module div_500K(clk,clk_60);
input clk;
output clk_60;
reg [18:0] count = 0;
always @ (posedge clk)
begin
count <= count + 1;
end
assign clk_60 = count[18];
endmodule
this code over and over and for some reason, I don't see it...it is
supposed to create a 60 Hz signal? Am I missing something? A 60 Hz's
period is half a period of a 30 Hz signal...I don't see the code below
doing that...
It is used to supply a signal(to another module) that changes every 17
ms to XOR with the common bias and encoded seven segment data for
correct operation with an LCD....
// module: div_500K.v
// This module divides the incoming clock(30 Hz) by 2^19 and outputs
the
// 19th bit of the counter as a 60 Hz clock, clk_60.
module div_500K(clk,clk_60);
input clk;
output clk_60;
reg [18:0] count = 0;
always @ (posedge clk)
begin
count <= count + 1;
end
assign clk_60 = count[18];
endmodule