Another newbie question

[Howler]

Hello all,

I am seeking some help with Verilog/vhdl. I am currently a student at
school and was given an assignment to write a program in verilog to
Implement Verilog program (module) to add two numbers (mini ALU) . The
external module should generate two numbers for example in a loop and
the sum should be calculated.

for i = 1; i < 100; i++
for j = 1; j < 100; j++
ADDModule(i,j,sum);
print (i, j, sum)

The coding is quite simple, however the few examples I have seen on
the web leave me with a few questions. We were told to use Xilinx's
product, however I am still not sure how the semantics work in this
environment. I come from an object oriented background so I am
thinking in terms of methods/functions. From the code I have seen
online verilog is similar to C. How do I use the testbench waveform?
Anyways any good resources out there or expert advise is appreciated.
Peace,

Omar

 

here are the two reqd code pieces put each in a seperate file then
compile each and simulate ipvectors.v

//adder.v
`timescale 1ns/1ns

module adder(a,b,sum,carry);

input [7:0] a,b;

output reg [7:0] sum;
output reg carry;


always @(a or b)
begin
{carry,sum} = a + b;
end

endmodule

//ipvectors.v
`timescale 1ns/1ns

module ip_vectors;

reg [7:0]i,j;
wire [7:0] s;
wire c;

adder adder1(i,j,s,c);

initial
begin
for(i=0;i<256;i=i+1)
begin
for(j=0;j<256;j=j+1)
#10;
end
end

endmodule

-Neo

 

[Howler]

zingafri...@yahoo.com wrote:

here are the two reqd code pieces put each in a seperate file then
compile each and simulate ipvectors.v

//adder.v
`timescale 1ns/1ns

module adder(a,b,sum,carry);

input [7:0] a,b;

output reg [7:0] sum;
output reg carry;


always @(a or b)
begin
{carry,sum} = a + b;
end

endmodule

//ipvectors.v
`timescale 1ns/1ns

module ip_vectors;

reg [7:0]i,j;
wire [7:0] s;
wire c;

adder adder1(i,j,s,c);

initial
begin
for(i=0;i<256;i=i+1)
begin
for(j=0;j<256;j=j+1)
#10;
end
end

endmodule

-Neo

 

[John McBride]

Hello Omar,

I see you are a computer programmer - and from an OO background, and you
want to know how does verilog fit into this paradigm?

Hardware description languages like verilog describe CONCURRENT
processes, however the processes themselves may be described in a
procedural algorithm. Like OOP there are events and event handlers,
however the language is a bit different.

Consider, for example the common event of a positive edge of clock, and
an event which responds to this:

always @(posedge CLOCK)
begin: some_process
....
end

always @(posedge CLOCK)
begin: another_process
....
end

...Both processes occur at the same time, on the event "positive edge of
signal CLOCK".


There are some concepts in HDL's though which do not have parallels in
software, examples:

VHDL: the difference between variables and signals
Verilog: the difference between blocking and non-blocking assignments

-these issues are related and concern the translation of a procedural
piece of HDL into a static piece of hardware.

For example, consider the description of a shift register:


module shift32 (SHIFT_IN, CLK, SHIFT_OUT);
input SHIFT_IN, CLK;
output SHIFT_OUT;

integer i;
reg [31:0] shift_reg;
reg SHIFT_OUT;

always @(posedge CLK)
begin: shift_register

for(i=1; i<32; i=i+1)
begin: shift_reg_element
shift_reg <= shift_reg[i-1];
end

shift_reg[0] <= SHIFT_IN;
SHIFT_OUT <= shift_reg[31];

end
endmodule


The line here in a loop:
shift_reg <= shift_reg[i-1];
means that there are 31 concurrent assignments from one signal to the
next, triggered by clock edge, hence inferring a shift register...
.... but if you drop the "<" sign something drastic happens - the shift
register disappears giving you a register only.

Why?
(Ans: http://www.asic-world.com/tidbits/blocking.html)

-This is just to give you a flavour of the HDL specific concepts that
you may not have encountered in pure software.


You also wanted to know about targetting Xilinx devices?
At the most basic level, you can simply test your verilog and make sure
it works, then go download Xilinx Web Pack
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sGlobalNavPick=PRODUCTS&sSecondaryNavPick=Design+Tools&key=DS-ISE-WEBPACK

It even comes with a free ModelSim Licence!

FPGA's are of varying complexity, so start off with a plane chip like
Spartan 3. Other chips are more complex, for example Virtex 2 Pro has
embedded microprocessors!

Use the inuitive Project Navigator tool flow to synthesise your design.
Now here is the snag - not all Verilog can be synthesised to a real
circuit, for example what does an infinite loop look like in hardware?
So, if the tools complain about something not being synthesisable don't
curse it, just ask on here.

You can see exactly how your design is implemented by opening FPGAEDITOR
and viewing the generated NCD file. You will see the intricate routing
of the FGPA, and how the logic is arranged in Look Up Tables, or native
specialised circuitry if available, such as embedded shift registers,
multipliers, ROMs, RAMs (and DSP if you use Virtex 4!).

I hope Verilog is an interesting challenge for you, and I hope you get
an appreciation of FPGA's!

John








Howler wrote:

Hello all,

I am seeking some help with Verilog/vhdl. I am currently a student at
school and was given an assignment to write a program in verilog to
Implement Verilog program (module) to add two numbers (mini ALU) . The
external module should generate two numbers for example in a loop and
the sum should be calculated.

for i = 1; i < 100; i++
for j = 1; j < 100; j++
ADDModule(i,j,sum);
print (i, j, sum)

The coding is quite simple, however the few examples I have seen on
the web leave me with a few questions. We were told to use Xilinx's
product, however I am still not sure how the semantics work in this
environment. I come from an object oriented background so I am
thinking in terms of methods/functions. From the code I have seen
online verilog is similar to C. How do I use the testbench waveform?
Anyways any good resources out there or expert advise is appreciated.
Peace,

Omar

 

[Carsten]

On Wed, 19 Jan 2005 20:40:09 GMT, John McBride
<rp.costellomacbride@ntlworld.ie> wrote:

Hello Omar,

I see you are a computer programmer - and from an OO background, and you
want to know how does verilog fit into this paradigm?

Hardware description languages like verilog describe CONCURRENT
processes, however the processes themselves may be described in a
procedural algorithm. Like OOP there are events and event handlers,
however the language is a bit different.
....

....

I hope Verilog is an interesting challenge for you, and I hope you get
an appreciation of FPGA's!

John

Hi John

Thank you for a verry nice post for all us beginners in HDL , that
knows C and a bit of TTL logic.

Wish there were a site dedicated to this ...

Regards
Carsten
Denmark

 

[Howler]

Carsten wrote:

On Wed, 19 Jan 2005 20:40:09 GMT, John McBride
rp.costellomacbride@ntlworld.ie> wrote:

Hello Omar,

I see you are a computer programmer - and from an OO background, and
you
want to know how does verilog fit into this paradigm?

Hardware description languages like verilog describe CONCURRENT
processes, however the processes themselves may be described in a
procedural algorithm. Like OOP there are events and event handlers,

however the language is a bit different.
...
...

I hope Verilog is an interesting challenge for you, and I hope you
get
an appreciation of FPGA's!

John

Hi John

Thank you for a verry nice post for all us beginners in HDL , that
knows C and a bit of TTL logic.

Wish there were a site dedicated to this ...

Regards
Carsten
Denmark

Yes, thanks to all who have replied to my post. I appreciate your
prompt and well thought out responses. Since my initial post I have
contacted my professor regarding verilog/vhdl. He pointed out a web
site that I will be referencing quite a bit. For any other newbies out
there such as myself the url is http://www.asic-world.com/ Talk to you
later.

Peace,

Omar