Another dumbo

[parag_paul@hotmail.com]

What is the meaning of delta's in simulation

 

[mjl296@hotmail.com]

On 28 Mar, 02:23, "parag_p...@hotmail.com" <parag_p...@hotmail.com>
wrote:

What is the meaning of delta's in simulation

So this is not a dumbo, but a good question related to how the
simulator works.

Verilog simulators are "event driven", which means that events are
scheduled to occur at a specific simulation time and are popped off
and processed in order. To avoid confusion just consider an event to
be a change in a signal's value. A delta time is an infinitesimal time
step used to separate events from one another, when the events occur
at the same simulation time but should still be popped off the event
queue in order.

To illustrate the point, imagine the following code.

always @(A)
begin
A <= ~A;
end

Here, the process is triggered by the first event on A (at time T ns)
and itself schedules another event on A in one delta cycle (time T ns
+ 1 delta). This triggers the process again at time T ns + 1 delta and
another event is then scheduled for time T ns + 2 delta.

This is called a delta-time loop and will lock up your simulation.

Delta times also has everything to do with the difference between
blocking and non-blocking assignments. A blocking assignment performs
the assignment immediately. A non-blocking assignment performs the
assignment after one delta time.

There are many subtlties about this and to fully predict the order of
sequencing I would need to look in the LRM, but hopefully this quick
summary should point you in the direction of the information that you
require.