Another discrepancy (LTspice/switchcad3)

[Robert Baer]

The results are way off.
The sense resistor is for a peak current of 240mA, the time when the
gate is supposed to turn off.
The current in the 1mH inductor is supposed to be a linear ramp from
zero to 240mA, and take about 2.3uSec for an inductor supply of 100V
(8.9uSec for 30V, 5.0uSec for 50V and 1.0uSec for 200V). These values
are from a real circuit, and seem to be reasonably close to calculated
values using E=-L*(dI/dT).
The current never gets into the ampere region(!!).
Furthermore, when the FET turns off, there should be a large, narrow
voltage pulse (not some variable wierd-shaped and slow rise waveform).
What is wrong? Code follows:

Version 4
SHEET 1 1000 680
WIRE -400 352 -400 -96
WIRE -272 80 -272 32
WIRE -272 224 -272 160
WIRE -272 256 -272 224
WIRE -272 432 -272 336
WIRE -176 528 -176 304
WIRE -176 608 -176 592
WIRE -160 -96 -400 -96
WIRE -160 144 -160 -16
WIRE -144 304 -176 304
WIRE -144 336 -144 304
WIRE -144 608 -176 608
WIRE -144 608 -144 480
WIRE -80 144 -160 144
WIRE -80 224 -272 224
WIRE -80 304 -144 304
WIRE 80 -96 -160 -96
WIRE 80 80 80 -96
WIRE 80 608 -144 608
WIRE 80 608 80 368
WIRE 80 640 80 608
WIRE 304 -96 80 -96
WIRE 304 144 240 144
WIRE 304 144 304 -96
WIRE 304 304 240 304
WIRE 304 384 304 304
WIRE 352 224 240 224
WIRE 352 320 352 224
WIRE 480 -112 480 -160
WIRE 544 320 352 320
WIRE 592 -160 480 -160
WIRE 592 80 528 80
WIRE 592 80 592 -160
WIRE 592 128 592 80
WIRE 592 224 592 208
WIRE 592 240 592 224
WIRE 592 384 304 384
WIRE 592 384 592 336
WIRE 592 416 592 384
WIRE 688 224 656 224
WIRE 688 352 688 224
WIRE 688 464 688 416
WIRE 704 224 688 224
WIRE 896 32 -272 32
WIRE 896 224 768 224
WIRE 896 224 896 32
WIRE 896 288 896 224
FLAG 80 640 0
FLAG -400 432 0
FLAG 592 496 0
FLAG 480 -32 0
FLAG 896 352 0
FLAG -272 432 0
FLAG 688 464 0
FLAG 528 144 0
SYMBOL voltage -400 336 R0
WINDOW 0 -46 6 Left 0
WINDOW 3 -70 87 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15V
SYMBOL nmos 544 240 R0
WINDOW 0 56 67 Left 0
WINDOW 3 -115 41 Left 0
SYMATTR InstName M1
SYMATTR Value IRF7343N
SYMBOL res 576 400 R0
SYMATTR InstName R1
SYMATTR Value 0.22
SYMBOL ind 576 112 R0
WINDOW 3 30 -1 Left 0
SYMATTR Value 1mH
SYMATTR InstName L1
SYMBOL voltage 480 -128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 100V
SYMBOL cap 880 288 R0
WINDOW 0 -45 -7 Left 0
WINDOW 3 -85 49 Left 0
SYMATTR InstName C4
SYMATTR Value 4700pF
SYMBOL diode 704 240 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName D1
SYMATTR Value MUR460
SYMBOL PowerProducts\\LT1619 80 224 R0
SYMATTR InstName U1
SYMBOL res -160 320 R0
SYMATTR InstName R2
SYMATTR Value 75K
SYMBOL cap -160 416 R0
SYMATTR InstName C1
SYMATTR Value 15nF
SYMBOL cap -192 528 R0
WINDOW 0 -27 -6 Left 0
WINDOW 3 -55 62 Left 0
SYMATTR InstName C2
SYMATTR Value 220pF
SYMBOL res -288 240 R0
SYMATTR InstName R3
SYMATTR Value 12.4K
SYMBOL res -288 64 R0
SYMATTR InstName R4
SYMATTR Value 49988K
SYMBOL res -176 -112 R0
SYMATTR InstName R5
SYMATTR Value 10K
SYMBOL diode 704 416 R180
WINDOW 0 24 72 Left 0
WINDOW 3 -98 -6 Left 0
SYMATTR InstName D2
SYMATTR Value MUR460
SYMBOL cap 656 208 R90
WINDOW 0 0 16 VBottom 0
WINDOW 3 34 9 VTop 0
SYMATTR InstName C3
SYMATTR Value 4700pF
SYMBOL cap 512 80 R0
WINDOW 0 -63 4 Left 0
WINDOW 3 -84 60 Left 0
SYMATTR InstName C5
SYMATTR Value 5.0ľF
TEXT 528 224 Left 0 ;N009
TEXT -312 664 Left 0 !.tran 0 25uSEC 0uSec 0.001uSEC
TEXT 448 408 Left 0 ;N006
TEXT 376 344 Left 0 ;N007

 

[Mike Engelhardt]

Robert,

The results are way off.

The simulation is probably right around correct. That
FET and diode have capacitance. Below is a working 1619
circuit you might use as stating point.

--Mike

--- 1619.asc ---


Version 4
SHEET 1 2528 1112
WIRE 944 1040 944 800
WIRE 976 960 976 880
WIRE 976 992 976 960
WIRE 1008 544 1008 512
WIRE 1008 656 1008 624
WIRE 1008 880 976 880
WIRE 1056 960 976 960
WIRE 1088 880 1072 880
WIRE 1152 512 1008 512
WIRE 1152 720 1152 512
WIRE 1184 880 1168 880
WIRE 1184 960 1120 960
WIRE 1184 960 1184 880
WIRE 1216 720 1152 720
WIRE 1216 800 944 800
WIRE 1216 880 1184 880
WIRE 1376 512 1152 512
WIRE 1376 656 1376 512
WIRE 1376 992 1376 944
WIRE 1552 720 1536 720
WIRE 1552 720 1552 640
WIRE 1584 640 1552 640
WIRE 1584 656 1584 640
WIRE 1584 736 1584 720
WIRE 1648 800 1536 800
WIRE 1696 512 1376 512
WIRE 1696 528 1696 512
WIRE 1696 704 1696 608
WIRE 1696 720 1696 704
WIRE 1696 880 1536 880
WIRE 1696 880 1696 816
WIRE 1696 896 1696 880
WIRE 1696 992 1696 976
WIRE 1776 704 1696 704
WIRE 1792 1040 944 1040
WIRE 1792 1040 1792 848
WIRE 1888 640 1584 640
WIRE 1888 704 1840 704
WIRE 1888 704 1888 640
WIRE 1888 736 1888 704
WIRE 1888 848 1792 848
WIRE 1888 848 1888 816
WIRE 1888 880 1888 848
WIRE 1888 976 1888 960
WIRE 2016 704 1888 704
WIRE 2016 816 2016 704
WIRE 2016 976 2016 880
WIRE 2128 704 2016 704
WIRE 2128 800 2128 704
WIRE 2128 976 2128 880
FLAG 2128 704 OUT
FLAG 1008 656 0
FLAG 2016 976 0
FLAG 2128 976 0
FLAG 1888 976 0
FLAG 976 992 0
FLAG 1376 992 0
FLAG 1696 992 0
FLAG 1584 736 0
SYMBOL IND 1680 512 R0
SYMATTR InstName L1
SYMATTR Value 12ľ
SYMBOL NMOS 1648 720 R0
WINDOW 0 60 20 Left 0
WINDOW 3 60 84 Left 0
SYMATTR InstName M1
SYMATTR Value Si9804DY
SYMBOL VOLTAGE 1008 528 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL cap 1120 944 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C2
SYMATTR Value 150p
SYMBOL cap 1072 864 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C4
SYMATTR Value .015ľ
SYMBOL RES 1680 880 R0
SYMATTR InstName R3
SYMATTR Value 0.014
SYMBOL res 1872 864 R0
SYMATTR InstName R2
SYMATTR Value 12.4K
SYMBOL res 1872 720 R0
SYMATTR InstName R1
SYMATTR Value 37.4K
SYMBOL res 1184 864 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R4
SYMATTR Value 25K
SYMBOL cap 1568 656 R0
SYMATTR InstName C7
SYMATTR Value .1ľ
SYMBOL polcap 2000 816 R0
SYMATTR InstName C6
SYMATTR Value 440ľ
SYMATTR SpiceLine Rser=0.065
SYMBOL POWERPRODUCTS\\LT1619 1376 800 R0
SYMATTR InstName U1
SYMBOL schottky 1776 720 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName D1
SYMATTR Value MBR735
SYMBOL res 2112 784 R0
SYMATTR InstName R5
SYMATTR Value 3
TEXT 1840 1024 Left 0 !.tran 4m startup



"Robert Baer" <robertbaer@earthlink.net> wrote in message
news:d8Lme.3891$MI4.26@newsread2.news.pas.earthlink.net...

The results are way off.
The sense resistor is for a peak current of 240mA, the time when the
gate is supposed to turn off.
The current in the 1mH inductor is supposed to be a linear ramp from
zero to 240mA, and take about 2.3uSec for an inductor supply of 100V
(8.9uSec for 30V, 5.0uSec for 50V and 1.0uSec for 200V). These values are
from a real circuit, and seem to be reasonably close to calculated values
using E=-L*(dI/dT).
The current never gets into the ampere region(!!).
Furthermore, when the FET turns off, there should be a large, narrow
voltage pulse (not some variable wierd-shaped and slow rise waveform).
What is wrong? Code follows:

Version 4
SHEET 1 1000 680
WIRE -400 352 -400 -96
WIRE -272 80 -272 32
WIRE -272 224 -272 160
WIRE -272 256 -272 224
WIRE -272 432 -272 336
WIRE -176 528 -176 304
WIRE -176 608 -176 592
WIRE -160 -96 -400 -96
WIRE -160 144 -160 -16
WIRE -144 304 -176 304
WIRE -144 336 -144 304
WIRE -144 608 -176 608
WIRE -144 608 -144 480
WIRE -80 144 -160 144
WIRE -80 224 -272 224
WIRE -80 304 -144 304
WIRE 80 -96 -160 -96
WIRE 80 80 80 -96
WIRE 80 608 -144 608
WIRE 80 608 80 368
WIRE 80 640 80 608
WIRE 304 -96 80 -96
WIRE 304 144 240 144
WIRE 304 144 304 -96
WIRE 304 304 240 304
WIRE 304 384 304 304
WIRE 352 224 240 224
WIRE 352 320 352 224
WIRE 480 -112 480 -160
WIRE 544 320 352 320
WIRE 592 -160 480 -160
WIRE 592 80 528 80
WIRE 592 80 592 -160
WIRE 592 128 592 80
WIRE 592 224 592 208
WIRE 592 240 592 224
WIRE 592 384 304 384
WIRE 592 384 592 336
WIRE 592 416 592 384
WIRE 688 224 656 224
WIRE 688 352 688 224
WIRE 688 464 688 416
WIRE 704 224 688 224
WIRE 896 32 -272 32
WIRE 896 224 768 224
WIRE 896 224 896 32
WIRE 896 288 896 224
FLAG 80 640 0
FLAG -400 432 0
FLAG 592 496 0
FLAG 480 -32 0
FLAG 896 352 0
FLAG -272 432 0
FLAG 688 464 0
FLAG 528 144 0
SYMBOL voltage -400 336 R0
WINDOW 0 -46 6 Left 0
WINDOW 3 -70 87 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15V
SYMBOL nmos 544 240 R0
WINDOW 0 56 67 Left 0
WINDOW 3 -115 41 Left 0
SYMATTR InstName M1
SYMATTR Value IRF7343N
SYMBOL res 576 400 R0
SYMATTR InstName R1
SYMATTR Value 0.22
SYMBOL ind 576 112 R0
WINDOW 3 30 -1 Left 0
SYMATTR Value 1mH
SYMATTR InstName L1
SYMBOL voltage 480 -128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 100V
SYMBOL cap 880 288 R0
WINDOW 0 -45 -7 Left 0
WINDOW 3 -85 49 Left 0
SYMATTR InstName C4
SYMATTR Value 4700pF
SYMBOL diode 704 240 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName D1
SYMATTR Value MUR460
SYMBOL PowerProducts\\LT1619 80 224 R0
SYMATTR InstName U1
SYMBOL res -160 320 R0
SYMATTR InstName R2
SYMATTR Value 75K
SYMBOL cap -160 416 R0
SYMATTR InstName C1
SYMATTR Value 15nF
SYMBOL cap -192 528 R0
WINDOW 0 -27 -6 Left 0
WINDOW 3 -55 62 Left 0
SYMATTR InstName C2
SYMATTR Value 220pF
SYMBOL res -288 240 R0
SYMATTR InstName R3
SYMATTR Value 12.4K
SYMBOL res -288 64 R0
SYMATTR InstName R4
SYMATTR Value 49988K
SYMBOL res -176 -112 R0
SYMATTR InstName R5
SYMATTR Value 10K
SYMBOL diode 704 416 R180
WINDOW 0 24 72 Left 0
WINDOW 3 -98 -6 Left 0
SYMATTR InstName D2
SYMATTR Value MUR460
SYMBOL cap 656 208 R90
WINDOW 0 0 16 VBottom 0
WINDOW 3 34 9 VTop 0
SYMATTR InstName C3
SYMATTR Value 4700pF
SYMBOL cap 512 80 R0
WINDOW 0 -63 4 Left 0
WINDOW 3 -84 60 Left 0
SYMATTR InstName C5
SYMATTR Value 5.0ľF
TEXT 528 224 Left 0 ;N009
TEXT -312 664 Left 0 !.tran 0 25uSEC 0uSec 0.001uSEC
TEXT 448 408 Left 0 ;N006
TEXT 376 344 Left 0 ;N007

 

[Helmut Sennewald]

----- Original Message -----
From: "Robert Baer" <robertbaer@earthlink.net>
Newsgroups: sci.electronics.cad
Sent: Monday, May 30, 2005 10:58 PM
Subject: Another discrepancy (LTspice/switchcad3)

The results are way off.
The sense resistor is for a peak current of 240mA, the time when the
gate is supposed to turn off.
The current in the 1mH inductor is supposed to be a linear ramp from
zero to 240mA, and take about 2.3uSec for an inductor supply of 100V
(8.9uSec for 30V, 5.0uSec for 50V and 1.0uSec for 200V). These values are
from a real circuit, and seem to be reasonably close to calculated values
using E=-L*(dI/dT).
The current never gets into the ampere region(!!).
Furthermore, when the FET turns off, there should be a large, narrow
voltage pulse (not some variable wierd-shaped and slow rise waveform).
What is wrong? Code follows:

Hello Robert,

1.
You have to choose parts which stands the 5kV you have set
as target voltage. Your parts don't handle 5kV.

2. A ratio of 50 (Vout/100V) is a factor of 10 too high,
especially because the supply is already at 100V.

3. The capacitance of the components will limit the max.
possible voltage also.

I recommend to use at least a voltage multiplier and
eventually a transformer instead of the coil.


Best regards,
Helmut

 

[Robert Baer]

Mike Engelhardt wrote:

Robert,


The results are way off.


The simulation is probably right around correct. That
FET and diode have capacitance. Below is a working 1619
circuit you might use as stating point.

--Mike

------------ SNIPped for brevity ---------
Adding a small capacitance has no effect.
Even altering the ideal inductor to a resistive inductor with
parallel capacitance has no effect.
I will try your 1619 circuit later; i use a different OS for mail/NGs
than for "fancy" work (different drives also).

 

[Robert Baer]

Helmut Sennewald wrote:

----- Original Message -----
From: "Robert Baer" <robertbaer@earthlink.net
Newsgroups: sci.electronics.cad
Sent: Monday, May 30, 2005 10:58 PM
Subject: Another discrepancy (LTspice/switchcad3)



The results are way off.
The sense resistor is for a peak current of 240mA, the time when the
gate is supposed to turn off.
The current in the 1mH inductor is supposed to be a linear ramp from
zero to 240mA, and take about 2.3uSec for an inductor supply of 100V
(8.9uSec for 30V, 5.0uSec for 50V and 1.0uSec for 200V). These values are
from a real circuit, and seem to be reasonably close to calculated values
using E=-L*(dI/dT).
The current never gets into the ampere region(!!).
Furthermore, when the FET turns off, there should be a large, narrow
voltage pulse (not some variable wierd-shaped and slow rise waveform).
What is wrong? Code follows:



Hello Robert,

1.
You have to choose parts which stands the 5kV you have set
as target voltage. Your parts don't handle 5kV.

2. A ratio of 50 (Vout/100V) is a factor of 10 too high,
especially because the supply is already at 100V.

3. The capacitance of the components will limit the max.
possible voltage also.

I recommend to use at least a voltage multiplier and
eventually a transformer instead of the coil.


Best regards,
Helmut




**1. The resistive divider is purposeley set for a larger than possible

voltage; to see what SPICE would do.

**2. The real circuit will output about 1000V with a 4V inductor supply;
i do not think this is relevant.

**3. For real parts, that is part of what happens. I tried making the
inductor more complex by adding a small series resistor and then
paralling that combo with a small capacitor. That modification made
absolutely zero difference.

**"4". If i take my P17/8-3C18 core and wind a "primary" of 56 turns and
then continue winding for another 73 turns (autoformer "secondary" of
129 turns), i get about 1800VDC with a doubler (very close to the
peak-to-peak voltage at xfmr output), with a 58Meg load (worst case PMT
divider); voltage at inductor "top" at 30V but can range from about 5V
to 200V (actually more than 200V but my bypass cap is rated at 200V).

** However, nothing you have mentioned addresses any of the major
discrepancies seen.

 

[Mike Engelhardt]

Robert,

The results are way off.

The simulation is probably right around correct.
That FET and diode have capacitance. .

Adding a small capacitance has no effect.

But that doesn't remove the capacitance that's already
swamping the circuit. The problem is the circuit design,
not the models.

I will try your 1619 circuit later

That one works. Notice that that SMPS topology is
a boost. To get higher output voltage, you might try
a tapped-inductor boost. That will reduce the voltage
rating required of the MOSFET and make the circuit
less sensitive to its capacitance. If you're not really
after a SMPS, but some high impedance high voltage,
you can probably get a chopped square wave working
into a diode voltage multiplier to work. That gets rid
of the problem of getting high impedance energy
storage inductors with little stray capacitance.

-Mike

 

[Mike Engelhardt]

Robert,

The results are way off.

The simulation is probably right around correct.
That FET and diode have capacitance.

Adding a small capacitance has no effect.


But that doesn't remove the capacitance that's already
swamping the circuit. The problem is the circuit design,
not the models.

There is no problem with the design. Both theory and
practice show that when a voltage is presented across
an inductor, that the current starts at zero and increases in the
standard L/R exponential "decay" to maximum, the
assumption is a linear inductor. Classical definition of
an inductor! The problem, is that the model does *not*
show that.

The current does ramp in the inductor when there's voltage
across it in the simulation. But the capacitance(and other
problems) prevents your circuit "design" from working.

Anyway, the "design" you have will not work. The simulation
is correct. If you build it, you will see the same waveforms
as in the simulation until the MOSFET dies due to being
over-voltaged. MOSFET catastrophic failure is not modeled
in LTspice in hope that this allows you to separately debug
the design and then find parts that don't die in the
circuit's operation.

And a pF or two cannot "swamp" anything here.

Not a pF or two. A 1.5nF for the MOSFET and 126pF
for the diode. It's hard to run a power SMPS down to
the tiny currents you're trying to do.

Regards,

--Mike

 

[Jim Thompson]

On Tue, 31 May 2005 21:00:23 GMT, "Mike Engelhardt" <nospam@spam.org>
wrote:

Robert,

[snip]

Anyway, the "design" you have will not work. The simulation
is correct. If you build it, you will see the same waveforms
as in the simulation until the MOSFET dies due to being
over-voltaged.
[snip]

Regards,

--Mike

"Designers" are what keep me in the "chips" ;-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Mike Engelhardt]

Robert,

The results are way off.

The simulation is probably right around correct.
That FET and diode have capacitance.

Adding a small capacitance has no effect.

But that doesn't remove the capacitance that's
already swamping the circuit.

And a pF or two cannot "swamp" anything here.

Not a pF or two. A 1.5nF for the MOSFET and 126pF
for the diode. It's hard to run a power SMPS down to
the tiny currents you're trying to do.

It might be illustrative to see your circuit operate
without the capacitance so severely swamping the
circuit. Below is your circuit except ideal switches
are used and the SMPS topology is corrected to a
true boost. This is not a practical circuit design,
because you can't buy the parts to make it go, but
a tapped boost topology would remove the problem
of the MOSFET capacitance.

Regards,

--Mike

Version 4
SHEET 1 1132 680
WIRE -432 -48 -432 -96
WIRE -432 96 -432 32
WIRE -352 96 -352 32
WIRE -352 224 -352 176
WIRE -352 256 -352 224
WIRE -352 368 -352 336
WIRE -240 368 -240 304
WIRE -240 528 -240 432
WIRE -160 -96 -432 -96
WIRE -160 -80 -160 -96
WIRE -160 144 -160 0
WIRE -144 304 -240 304
WIRE -144 336 -144 304
WIRE -144 432 -144 416
WIRE -144 528 -240 528
WIRE -144 528 -144 496
WIRE -80 144 -160 144
WIRE -80 224 -352 224
WIRE -80 304 -144 304
WIRE 80 -96 -160 -96
WIRE 80 80 80 -96
WIRE 80 528 -144 528
WIRE 80 528 80 368
WIRE 80 560 80 528
WIRE 256 -96 80 -96
WIRE 256 144 240 144
WIRE 256 144 256 -96
WIRE 304 224 240 224
WIRE 304 272 288 272
WIRE 352 64 352 -160
WIRE 352 176 352 144
WIRE 352 208 352 176
WIRE 352 304 240 304
WIRE 352 304 352 288
WIRE 352 320 352 304
WIRE 352 416 352 400
WIRE 416 -160 352 -160
WIRE 416 -144 416 -160
WIRE 416 -32 416 -64
WIRE 432 176 352 176
WIRE 544 32 -352 32
WIRE 544 176 496 176
WIRE 544 176 544 32
WIRE 544 208 544 176
WIRE 544 304 544 272
FLAG 80 560 0
FLAG -432 96 0
FLAG 352 416 0
FLAG 416 -32 0
FLAG 544 304 0
FLAG -352 368 0
FLAG 288 272 0
SYMBOL voltage -432 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15V
SYMBOL res 336 304 R0
SYMATTR InstName R1
SYMATTR Value 0.22
SYMBOL ind 336 48 R0
WINDOW 3 36 72 Left 0
SYMATTR Value 1mH
SYMATTR InstName L1
SYMBOL voltage 416 -160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 100V
SYMBOL cap 528 208 R0
SYMATTR InstName C4
SYMATTR Value 470p
SYMBOL diode 432 192 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName D1
SYMATTR Value X
SYMBOL LT1619 80 224 R0
SYMATTR InstName U1
SYMBOL res -160 320 R0
SYMATTR InstName R2
SYMATTR Value 75K
SYMBOL cap -160 432 R0
SYMATTR InstName C1
SYMATTR Value 15nF
SYMBOL cap -256 368 R0
SYMATTR InstName C2
SYMATTR Value 220pF
SYMBOL res -368 240 R0
SYMATTR InstName R3
SYMATTR Value 12.4K
SYMBOL res -368 80 R0
SYMATTR InstName R4
SYMATTR Value 49988K
SYMBOL res -176 -96 R0
SYMATTR InstName R5
SYMATTR Value 10K
SYMBOL sw 352 304 M180
SYMATTR InstName S1
TEXT 112 504 Left 0 !.tran 5m startup
TEXT 112 536 Left 0 !.model X D(Ron=1 Roff=1T)
TEXT 112 568 Left 0 !.model SW SW(Ron=1 Roff=1G Vt=5 Vh=-4)

 

[Robert Baer]

Mike Engelhardt wrote:

Robert,


The results are way off.

The simulation is probably right around correct.
That FET and diode have capacitance.

Adding a small capacitance has no effect.


But that doesn't remove the capacitance that's already
swamping the circuit. The problem is the circuit design,
not the models.

There is no problem with the design. Both theory and
practice show that when a voltage is presented across
an inductor, that the current starts at zero and increases in the
standard L/R exponential "decay" to maximum, the
assumption is a linear inductor. Classical definition of
an inductor! The problem, is that the model does *not*
show that.


The current does ramp in the inductor when there's voltage
across it in the simulation. But the capacitance(and other
problems) prevents your circuit "design" from working.

Anyway, the "design" you have will not work. The simulation
is correct. If you build it, you will see the same waveforms
as in the simulation until the MOSFET dies due to being
over-voltaged. MOSFET catastrophic failure is not modeled
in LTspice in hope that this allows you to separately debug
the design and then find parts that don't die in the
circuit's operation.


And a pF or two cannot "swamp" anything here.


Not a pF or two. A 1.5nF for the MOSFET and 126pF
for the diode. It's hard to run a power SMPS down to
the tiny currents you're trying to do.

Regards,

--Mike


I had thought that i made it clear that i have a *working* circuit.

Neither my model nor the "1619" model show a current ramp, period.
I took a simple test fixture that uses a FET with the drain to a fat
wire just long enough for a Tek current probe, then to the test
inductor, then to bypassing, where the inductor supply voltage is applied.
The gate is driven by an HP3312A waveform generator; adjustable rep
rate and pulse width.
Using a 10uH inductor (closest i had to the 12uH in the "1619"
model), and a 3.30V supply, i saw the following:
1) IRFBG20, 1000V rating, "miller" 22nCoul: linear current *ramp* to
600nSec, 60ma at 300nSec. Gate off at 500nSec was "slow" with a sloppy
flyback 20V rounded pulse.
2) IRLZ24N, 55V rating, "miller" 8.5nCoul: linear current *ramp* to
600nSec, 70ma at 300nSec. Gate off at 500nSec was fairly snappy with a
classic flyback 34V flattish pulse.
Case #2 works closer to theory for two reasons: a) the FET is turned
on harder with a 10V gate drive because it is a logic FET, and b) lower
miller capacitance makes for faster turnoff.

The models show *square waves* !!
The models show *AMPS* of current !!
The model does not show anything near reality!
The classic definition of an inductor is a (linear) component that
opposes a change of current.

 

[Robert Baer]

Jim Thompson wrote:

On Tue, 31 May 2005 21:00:23 GMT, "Mike Engelhardt" <nospam@spam.org
wrote:


Robert,


[snip]

Anyway, the "design" you have will not work. The simulation
is correct. If you build it, you will see the same waveforms
as in the simulation until the MOSFET dies due to being
over-voltaged.

[snip]

Regards,

--Mike



"Designers" are what keep me in the "chips" ;-)

...Jim Thompson
Please be kind to read my response to Mike ("above").

If you can tell me what i did wrong in the model, please let me know.
Once the model shows real current ramping in an inductor, then i
think that the rest will be OK.

 

[Jim Thompson]

On Tue, 31 May 2005 21:42:58 GMT, Robert Baer
<robertbaer@earthlink.net> wrote:

Jim Thompson wrote:

On Tue, 31 May 2005 21:00:23 GMT, "Mike Engelhardt" <nospam@spam.org
wrote:


Robert,


[snip]

Anyway, the "design" you have will not work. The simulation
is correct. If you build it, you will see the same waveforms
as in the simulation until the MOSFET dies due to being
over-voltaged.

[snip]

Regards,

--Mike



"Designers" are what keep me in the "chips" ;-)

...Jim Thompson
Please be kind to read my response to Mike ("above").
If you can tell me what i did wrong in the model, please let me know.
Once the model shows real current ramping in an inductor, then i
think that the rest will be OK.

Have you checked your _simulated_ schematic against the hardware?

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Helmut Sennewald]

"Robert Baer" <robertbaer@earthlink.net> schrieb im Newsbeitrag
news:76Xme.29$W77.9@newsread3.news.pas.earthlink.net...

Helmut Sennewald wrote:

----- Original Message -----
From: "Robert Baer" <robertbaer@earthlink.net
Newsgroups: sci.electronics.cad
Sent: Monday, May 30, 2005 10:58 PM
Subject: Another discrepancy (LTspice/switchcad3)

The results are way off.
The sense resistor is for a peak current of 240mA, the time when the
gate is supposed to turn off.
The current in the 1mH inductor is supposed to be a linear ramp from
zero to 240mA, and take about 2.3uSec for an inductor supply of 100V
(8.9uSec for 30V, 5.0uSec for 50V and 1.0uSec for 200V). These values
are from a real circuit, and seem to be reasonably close to calculated
values using E=-L*(dI/dT).
The current never gets into the ampere region(!!).
Furthermore, when the FET turns off, there should be a large, narrow
voltage pulse (not some variable wierd-shaped and slow rise waveform).
What is wrong? Code follows:



Hello Robert,

1.
You have to choose parts which stands the 5kV you have set
as target voltage. Your parts don't handle 5kV.

2. A ratio of 50 (Vout/100V) is a factor of 10 too high,
especially because the supply is already at 100V.

3. The capacitance of the components will limit the max.
possible voltage also.

I recommend to use at least a voltage multiplier and
eventually a transformer instead of the coil.


Best regards,
Helmut




**1. The resistive divider is purposeley set for a larger than possible
voltage; to see what SPICE would do.

**2. The real circuit will output about 1000V with a 4V inductor supply; i
do not think this is relevant.

**3. For real parts, that is part of what happens. I tried making the
inductor more complex by adding a small series resistor and then paralling
that combo with a small capacitor. That modification made absolutely zero
difference.

**"4". If i take my P17/8-3C18 core and wind a "primary" of 56 turns and
then continue winding for another 73 turns (autoformer "secondary" of 129
turns), i get about 1800VDC with a doubler (very close to the
peak-to-peak voltage at xfmr output), with a 58Meg load (worst case PMT
divider); voltage at inductor "top" at 30V but can range from about 5V to
200V (actually more than 200V but my bypass cap is rated at 200V).

** However, nothing you have mentioned addresses any of the major
discrepancies seen.

Hello Robert,
I did some more simulations with some components changed to get
more reliable results.
Maybe I see now what you mean with wrong pulses.
My simulation has shown double pulses at the gate output of
the LT1619 where I hadn't expected it.

I have sent my results to Mike.
Let's see what he will tell me.

Best regards,
Helmut

 

[Helmut Sennewald]

"Helmut Sennewald" <helmutsennewald@t-online.de> schrieb im Newsbeitrag
news:d7imh7$vhi$04$1@news.t-online.com...

"Robert Baer" <robertbaer@earthlink.net> schrieb im Newsbeitrag
news:76Xme.29$W77.9@newsread3.news.pas.earthlink.net...
Helmut Sennewald wrote:

----- Original Message -----
From: "Robert Baer" <robertbaer@earthlink.net
Newsgroups: sci.electronics.cad
Sent: Monday, May 30, 2005 10:58 PM
Subject: Another discrepancy (LTspice/switchcad3)

The results are way off.
The sense resistor is for a peak current of 240mA, the time when the
gate is supposed to turn off.
The current in the 1mH inductor is supposed to be a linear ramp from
zero to 240mA, and take about 2.3uSec for an inductor supply of 100V
(8.9uSec for 30V, 5.0uSec for 50V and 1.0uSec for 200V). These values
are from a real circuit, and seem to be reasonably close to calculated
values using E=-L*(dI/dT).
The current never gets into the ampere region(!!).
Furthermore, when the FET turns off, there should be a large, narrow
voltage pulse (not some variable wierd-shaped and slow rise waveform).
What is wrong? Code follows:



Hello Robert,

1.
You have to choose parts which stands the 5kV you have set
as target voltage. Your parts don't handle 5kV.

2. A ratio of 50 (Vout/100V) is a factor of 10 too high,
especially because the supply is already at 100V.

3. The capacitance of the components will limit the max.
possible voltage also.

I recommend to use at least a voltage multiplier and
eventually a transformer instead of the coil.


Best regards,
Helmut




**1. The resistive divider is purposeley set for a larger than possible
voltage; to see what SPICE would do.

**2. The real circuit will output about 1000V with a 4V inductor supply;
i do not think this is relevant.

**3. For real parts, that is part of what happens. I tried making the
inductor more complex by adding a small series resistor and then
paralling that combo with a small capacitor. That modification made
absolutely zero difference.

**"4". If i take my P17/8-3C18 core and wind a "primary" of 56 turns and
then continue winding for another 73 turns (autoformer "secondary" of 129
turns), i get about 1800VDC with a doubler (very close to the
peak-to-peak voltage at xfmr output), with a 58Meg load (worst case PMT
divider); voltage at inductor "top" at 30V but can range from about 5V to
200V (actually more than 200V but my bypass cap is rated at 200V).

** However, nothing you have mentioned addresses any of the major
discrepancies seen.

Hello Robert,
I did some more simulations with some components changed to get
more reliable results.
Maybe I see now what you mean with wrong pulses.
My simulation has shown double pulses at the gate output of
the LT1619 where I hadn't expected it.

I have sent my results to Mike.
Let's see what he will tell me.

Best regards,
Helmut

Hello Robert,

I already have got an answer from Mike. He told me
that these complex output pulses may be caused by different
reasons.

Best regards,
Helmut

------- Begin answer from Mike --------

That happens in really bad SMPS designs.
There's lots of ways you can get double/triple
pulses that are due to design flaw(s).
You have to deal with minimum on time,
maximum off time, slope compensation,
capacitive current spikes, blanking times,
and loop instabilities. SMPS have all sorts
of non-linear oscillation modes.

-------- End answer from mike -------------

 

[Mike Engelhardt]

Robert,

The results are way off.

The simulation is probably right around correct.
That FET and diode have capacitance.

Adding a small capacitance has no effect.

But that doesn't remove the capacitance that's
already swamping the circuit.

And a pF or two cannot "swamp" anything here.

Not a pF or two. A 1.5nF for the MOSFET and 126pF
for the diode. It's hard to run a power SMPS down to
the tiny currents you're trying to do.

I had thought that i made it clear that i have

That wasn't clear to me because the circuit you
posted clearly does not work.

The models show *square waves* !!
The models show *AMPS* of current !!
The model does not show anything near reality!

The difference is that you are using a different
MOSFET in simulation then the bench. The simulation
results would agree with using a the MOSFET you have
on that schematic you posted. Now you're here talking
about different MOSFETs.

LTspice is showing what reality would look like for the
parts you have in the schematic. Your bench circuit is
entirely different. The schematic is totally shorted
out with capacitance, your bench circuit apparently
not. See the corrected schematic I posted with
capacitance-free switches.

The classic definition of an inductor is a (linear)
component that opposes a change of current.

And the simulation you posted does show that. But you
have to look at the current in the inductor and
the voltage across it. Neither the sense resistor
nor the switch current will follow that ramp, because
capacitive displacement currents swamp the inductor
current ramp.

--Mike

 

[Mike Engelhardt]

Helmut,

I did some more simulations with some components
changed to get more reliable results. Maybe I
see now what you mean with wrong pulses.
My simulation has shown double pulses at the gate
output of the LT1619 where I hadn't expected it.

I have sent my results to Mike.
Let's see what he will tell me.

That's what happens with really poorly designed
SMPS's. There's lots of ways you can get
double/triple pulses that are due to design
flaws(s). You have to deal with min and max
on/off times, slope compensation(which nearly
swaps Robert's current slope with the 1mH
inductor moving the low frequency compensation
pretty close to voltage mode), and loop
instablies near the switching frequency. SMPS
have all sorts of non-linear oscillation modes.

But now it looks like the problem is that Robert
is using a different MOSFET on the bench than
in the schematic.

--Mike

 

[Robert Baer]

Jim Thompson wrote:

On Tue, 31 May 2005 21:42:58 GMT, Robert Baer
robertbaer@earthlink.net> wrote:


Jim Thompson wrote:


On Tue, 31 May 2005 21:00:23 GMT, "Mike Engelhardt" <nospam@spam.org
wrote:



Robert,


[snip]


Anyway, the "design" you have will not work. The simulation
is correct. If you build it, you will see the same waveforms
as in the simulation until the MOSFET dies due to being
over-voltaged.

[snip]


Regards,

--Mike



"Designers" are what keep me in the "chips" ;-)

...Jim Thompson

Please be kind to read my response to Mike ("above").
If you can tell me what i did wrong in the model, please let me know.
Once the model shows real current ramping in an inductor, then i
think that the rest will be OK.


Have you checked your _simulated_ schematic against the hardware?

...Jim Thompson
Absolutely.

I went further; i made a simple model for TopSpice and it works; the
same model for LTspice/Switchcad3 does not.
Now one may bitch that the FET used in the LTspice case is not the
same, but that is not a relevant arguement.
I "proved" that by my test fixture using first a 1000V FET (IRFBG20)
and then a logic FET (IRLZ24N).
Practice meets theory; a *ramp* of current when the gate is driven,
and a *pulse* of voltage right after the FET turns off.
No junk square waves, no tens of amps in the drain.

*** TopSpice ***
SWMODE MOSFET TopSpice 1993 rev 2.6 (for DOS)
..OPTIONS ACCT LIST NODE OPTS LIMPTS=2000000
..TEMP 27
* ini amp Td Tr Tf PW Per
VG 1 0 PULSE( 0 10 0us 0.01us 0.01us 19.98us 100us)
VL 0 5 -10V
LL 5 4 1000UH
* D G S
X1 4 1 0 IRFBG20
..TRAN 0.1US 25US
..PRINT TRAN/ALL V(4) I(VL)
..SUBCKT IRFBG20 1 2 3
**************************************
* Model Generated by MODPEX *
*Copyright(c) Symmetry Design Systems*
* All Rights Reserved *
* UNPUBLISHED LICENSED SOFTWARE *
* Contains Proprietary Information *
* Which is The Property of *
* SYMMETRY OR ITS LICENSORS *
*Commercial Use or Resale Restricted *
* by Symmetry License Agreement *
**************************************
* Model generated on Mar 14, 97
* MODEL FORMAT: SPICE3
* Symmetry POWER MOS Model (Version 1.0)
* External Node Designations
* Node 1 -> Drain
* Node 2 -> Gate
* Node 3 -> Source
M1 9 7 8 8 MM L=100u W=100u
* Default values used in MM:
* The voltage-dependent capacitances are
* not included. Other default values are:
* RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0
..MODEL MM NMOS LEVEL=1 IS=1e-32
+VTO=4.19558 LAMBDA=0.00317546 KP=1.10594
+CGSO=4.97244e-06 CGDO=1e-11
RS 8 3 0.226968
D1 3 1 MD
..MODEL MD D IS=2.60701e-11 RS=0.0402674 N=1.17581 BV=1000
+IBV=0.00025 EG=1 XTI=1 TT=0
+CJO=4.31956e-10 VJ=2.22169 M=0.9 FC=0.5
***RDS 3 1 1e+07
RD 9 1 6.20884
RG 2 7 4.12
D2 4 5 MD1
* Default values used in MD1:
* RS=0 EG=1.11 XTI=3.0 TT=0
* BV=infinite IBV=1mA
..MODEL MD1 D IS=1e-32 N=50
+CJO=1.29076e-09 VJ=0.888177 M=0.9 FC=1e-08
D3 0 5 MD2
* Default values used in MD2:
* EG=1.11 XTI=3.0 TT=0 CJO=0
* BV=infinite IBV=1mA
..MODEL MD2 D IS=1e-10 N=0.456748 RS=3e-06
RL 5 10 1
FI2 7 9 VFI2 -1
VFI2 4 0 0
EV16 10 0 9 7 1
CAP 11 10 1.29076e-09
FI1 7 9 VFI1 -1
VFI1 11 6 0
RCAP 6 10 1
D4 0 6 MD3
* Default values used in MD3:
* EG=1.11 XTI=3.0 TT=0 CJO=0
* RS=0 BV=infinite IBV=1mA
..MODEL MD3 D IS=1e-10 N=0.456748
..ENDS IRFBG20
..SAVE
..END
**************

*** for LTspice/Switchcad3 ***
Version 4
SHEET 1 880 680
WIRE -176 208 -176 112
WIRE -48 352 -48 320
WIRE 80 320 -48 320
WIRE 128 112 -176 112
WIRE 128 240 128 192
FLAG -176 288 0
FLAG 128 336 0
FLAG -48 432 0
SYMBOL voltage -176 304 R180
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value -10V
SYMBOL ind 112 96 R0
SYMATTR InstName L1
SYMATTR Value 1000ľH
SYMBOL nmos 80 240 R0
SYMATTR InstName M1
SYMBOL voltage -48 336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 10 0 0.01U 0.01U 19.98U 100U)
TEXT 144 224 Left 0 ;N003
TEXT -258 506 Left 0 !.tran 0 25US 0 .1U
TEXT -176 72 Left 0 ;** PRINT TRAN/ALL V(N003) I(V1)
***************

 

[Jim Thompson]

I'm busy, so it may take a few days, but I'll give it a try in PSpice.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Robert Baer]

Helmut Sennewald wrote:

"Helmut Sennewald" <helmutsennewald@t-online.de> schrieb im Newsbeitrag
news:d7imh7$vhi$04$1@news.t-online.com...

"Robert Baer" <robertbaer@earthlink.net> schrieb im Newsbeitrag
news:76Xme.29$W77.9@newsread3.news.pas.earthlink.net...

Helmut Sennewald wrote:


----- Original Message -----
From: "Robert Baer" <robertbaer@earthlink.net
Newsgroups: sci.electronics.cad
Sent: Monday, May 30, 2005 10:58 PM
Subject: Another discrepancy (LTspice/switchcad3)


The results are way off.
The sense resistor is for a peak current of 240mA, the time when the
gate is supposed to turn off.
The current in the 1mH inductor is supposed to be a linear ramp from
zero to 240mA, and take about 2.3uSec for an inductor supply of 100V
(8.9uSec for 30V, 5.0uSec for 50V and 1.0uSec for 200V). These values
are from a real circuit, and seem to be reasonably close to calculated
values using E=-L*(dI/dT).
The current never gets into the ampere region(!!).
Furthermore, when the FET turns off, there should be a large, narrow
voltage pulse (not some variable wierd-shaped and slow rise waveform).
What is wrong? Code follows:



Hello Robert,

1.
You have to choose parts which stands the 5kV you have set
as target voltage. Your parts don't handle 5kV.

2. A ratio of 50 (Vout/100V) is a factor of 10 too high,
especially because the supply is already at 100V.

3. The capacitance of the components will limit the max.
possible voltage also.

I recommend to use at least a voltage multiplier and
eventually a transformer instead of the coil.


Best regards,
Helmut





**1. The resistive divider is purposeley set for a larger than possible
voltage; to see what SPICE would do.

**2. The real circuit will output about 1000V with a 4V inductor supply;
i do not think this is relevant.

**3. For real parts, that is part of what happens. I tried making the
inductor more complex by adding a small series resistor and then
paralling that combo with a small capacitor. That modification made
absolutely zero difference.

**"4". If i take my P17/8-3C18 core and wind a "primary" of 56 turns and
then continue winding for another 73 turns (autoformer "secondary" of 129
turns), i get about 1800VDC with a doubler (very close to the
peak-to-peak voltage at xfmr output), with a 58Meg load (worst case PMT
divider); voltage at inductor "top" at 30V but can range from about 5V to
200V (actually more than 200V but my bypass cap is rated at 200V).

** However, nothing you have mentioned addresses any of the major
discrepancies seen.

Hello Robert,
I did some more simulations with some components changed to get
more reliable results.
Maybe I see now what you mean with wrong pulses.
My simulation has shown double pulses at the gate output of
the LT1619 where I hadn't expected it.

I have sent my results to Mike.
Let's see what he will tell me.

Best regards,
Helmut


Hello Robert,

I already have got an answer from Mike. He told me
that these complex output pulses may be caused by different
reasons.

Best regards,
Helmut

------- Begin answer from Mike --------

That happens in really bad SMPS designs.
There's lots of ways you can get double/triple
pulses that are due to design flaw(s).
You have to deal with minimum on time,
maximum off time, slope compensation,
capacitive current spikes, blanking times,
and loop instabilities. SMPS have all sorts
of non-linear oscillation modes.

-------- End answer from mike -------------




Errr...I have reduced the problem to the most simple possible; a FET

driving an inductor. *No* SMPS, just a basic circuit.
*Same* problem.
See an earlier response with that simple circuit *working* in
TopSpice (1mH, 20uSec, 10V), virtually identical to practice, but
garbage square waves in LTspice/switchcad3.
As i mentioned earlier, i used my simple test fixture (to emulate the
"1619" example) using a 10uH inductor and 3.3V supply and got a *ramp*
of current to a few hundred mA - just like theory (and the *definition*
of an inductor). But LTspice/switchcad3 gives square waves.
Different inductance and time scales, but the same result for practice.
Modelling with a given SPICE program is consistent for that program,
but TopSpice echos practice and the other does not.
I guess for this, i will have to scrap LTspice/switchcad3.

 

[Robert Baer]

Mike Engelhardt wrote:

Robert,


The results are way off.

The simulation is probably right around correct.
That FET and diode have capacitance.


Adding a small capacitance has no effect.

But that doesn't remove the capacitance that's
already swamping the circuit.

And a pF or two cannot "swamp" anything here.

Not a pF or two. A 1.5nF for the MOSFET and 126pF
for the diode. It's hard to run a power SMPS down to
the tiny currents you're trying to do.

I had thought that i made it clear that i have


That wasn't clear to me because the circuit you
posted clearly does not work.


The models show *square waves* !!
The models show *AMPS* of current !!
The model does not show anything near reality!


The difference is that you are using a different
MOSFET in simulation then the bench. The simulation
results would agree with using a the MOSFET you have
on that schematic you posted. Now you're here talking
about different MOSFETs.

LTspice is showing what reality would look like for the
parts you have in the schematic. Your bench circuit is
entirely different. The schematic is totally shorted
out with capacitance, your bench circuit apparently
not. See the corrected schematic I posted with
capacitance-free switches.


The classic definition of an inductor is a (linear)
component that opposes a change of current.


And the simulation you posted does show that. But you
have to look at the current in the inductor and
the voltage across it. Neither the sense resistor
nor the switch current will follow that ramp, because
capacitive displacement currents swamp the inductor
current ramp.

--Mike


Oh, then no matter what inductor i use, no matter what the time scale

i use, that is the excuse?
Put a resistor in series with the inductor and see what that current
is; you will get the *same* square wave as every where else.
BTW, i originally used a FET from those available in the software
package, and not an ideal one - same result.
An ideal switch VS a slow, high capacitance FET like the IRFBG20
makes little difference on the workbench; current thru an inductor will
be a ramp - pure and simple.
My tests show the "slow" turnoff, wider flyback pulse with no "flat"
top when using the IRFBG20.
The same test fixture, with everything else the same - but using an
IRLZ24N shows a reasonably fast turnoff, a reasonably narrow flyback
pulse, and the classic flat top.
The model shows only square waves.
No ramp, no flyback pulse!
With an ideal switch, one cannot say that the inductor energy "got
swampped" to explain away the loss of a flyback pulse.
Be at least a little realistic...