Guest
There have been a number of attempts of linking Python and Verilog. APVM
embeds the
Python interpreter in Verilog using the VPI interface. It also presents an
object-oriented
interface to storing instance data and registering simulation callbacks.
This package has
a few other features that help simplify writing PLI applications and has
been shown to work
with Icarus, NC, Modelsim and VCS.
This initial release (0.10) has a short paper describing its design
philosophy and is distributed
with a number of useful and illustrative examples. The release is hosted at
Source Forge at
http://apvm.sourceforge.net
-T
embeds the
Python interpreter in Verilog using the VPI interface. It also presents an
object-oriented
interface to storing instance data and registering simulation callbacks.
This package has
a few other features that help simplify writing PLI applications and has
been shown to work
with Icarus, NC, Modelsim and VCS.
This initial release (0.10) has a short paper describing its design
philosophy and is distributed
with a number of useful and illustrative examples. The release is hosted at
Source Forge at
http://apvm.sourceforge.net
-T