ANNOUNCE: MyHDL 0.4

[Jan Decaluwe]

I am happy to announce the release of MyHDL 0.4. MyHDL is a Python
package for using Python as a hardware description & verification
language.

MyHDL 0.4 supports the automatic conversion of a subset of MyHDL code
to synthesizable Verilog code. This feature provides a direct path
from Python to an FPGA or ASIC implementation.

For the details on the release, go here:

http://jandecaluwe.com/Tools/MyHDL/whatsnew04/whatsnew04.html

For a general overview and starting point, go here:

http://jandecaluwe.com/Tools/MyHDL/Overview.html

Regards, Jan

--
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
Python is fun, and now you can design hardware with it:
http://jandecaluwe.com/Tools/MyHDL/Overview.html

 

[Thomas Heller]

Jan Decaluwe <jan@jandecaluwe.com> writes:

I am happy to announce the release of MyHDL 0.4. MyHDL is a Python
package for using Python as a hardware description & verification
language.

MyHDL 0.4 supports the automatic conversion of a subset of MyHDL code
to synthesizable Verilog code.

Very cool, but do you intend to add VHDL generation at some time?

Although it seems it would be better I had learned verilog instead.

Thomas

 

[Jan Decaluwe]

Thomas Heller wrote:

Jan Decaluwe <jan@jandecaluwe.com> writes:


I am happy to announce the release of MyHDL 0.4. MyHDL is a Python
package for using Python as a hardware description & verification
language.

MyHDL 0.4 supports the automatic conversion of a subset of MyHDL code
to synthesizable Verilog code.


Very cool, but do you intend to add VHDL generation at some time?

Although it seems it would be better I had learned verilog instead.

Verilog is quite allright as a back-end format

VHDL output - no plans, for the following reasons:

1. I would need an open-source VHDL simulator *with PLI support*
An Icarus for VHDL, let's say (thanks, Stephen Williams!). To verify
output conversion, it is essential to have co-simulation. As far
as I know, this is just not there for VHDL.

2. The fact that Verilog co-simulation and conversion works,
demonstrates that "it can be done". There *is* now a path to
implementation using an intermediate format that any
EDA tool will understand. For me personally and for
the myhdl technology it makes more sense to tackle other areas
(especially verification) than "to do it again". That having
said, I welcome any effort and any help from others to
fill in missing functionality, such as VHDL support.

Of course, I'll take back all of these points if sponsors show up.

Regards, Jan

--
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
Python is fun, and now you can design hardware with it:
http://jandecaluwe.com/Tools/MyHDL/Overview.html