S
Swapnajit Mittra
Guest
They have been always there, but you never noticed them (except, may be
while making higher level modules). In this month's article, Project
VeriPage looks into how SystemVerilog puts you in the driving seat to
control the connectivity, a.k.a. 'Interface', between two modules and
how you can abstract it to your advantage. By separating the internal
design and port connectivity of a module, the article shows you how to
take advantage of this separation.
http://www.project-veripage.com/interface_1.php
[For automatic updates, subscribe to Project VeriPage newsletter:
<URL: http://www.project-veripage.com/list/?p=subscribe&id=1>]
while making higher level modules). In this month's article, Project
VeriPage looks into how SystemVerilog puts you in the driving seat to
control the connectivity, a.k.a. 'Interface', between two modules and
how you can abstract it to your advantage. By separating the internal
design and port connectivity of a module, the article shows you how to
take advantage of this separation.
http://www.project-veripage.com/interface_1.php
[For automatic updates, subscribe to Project VeriPage newsletter:
<URL: http://www.project-veripage.com/list/?p=subscribe&id=1>]