S
Suraj N. Kurapati
Guest
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Ruby-VPI is a Ruby interface to Verilog VPI. It lets you create
complex Verilog test benches easily and wholly in Ruby.
http://ruby-vpi.rubyforge.org
= Version 0.6 (2006-05-25)
== Summary
This major release adds a comprehensive user manual, upgrades from
make to Rake[http://rake.rubyforge.org], and improves the test
generation tool.
== Details
* A comprehensive user manual, written in DocBook-XML, has been added.
* Rake has replaced the role of +make+. All makefiles have been
converted accordingly.
* The test generation tool now generates multiple files (runner,
bench, design, spec) and makes backups of existing files. See its
help information for details.
* Support for RSpec 0.5.4 has been added.
* The counter example now makes use of RSpec.
* Tested and developed using:
* Ruby 1.8.4 and Icarus Verilog 0.8 on i686 GNU/Linux
* Ruby 1.8.4 and Mentor Modelsim 6.1d on x86_64 GNU/Linux
== Acknowledgment
* Thanks to Jose Renau for solving the problem of strange delays
that occurred whenever a design was reset.
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Hash: SHA1
Ruby-VPI is a Ruby interface to Verilog VPI. It lets you create
complex Verilog test benches easily and wholly in Ruby.
http://ruby-vpi.rubyforge.org
= Version 0.6 (2006-05-25)
== Summary
This major release adds a comprehensive user manual, upgrades from
make to Rake[http://rake.rubyforge.org], and improves the test
generation tool.
== Details
* A comprehensive user manual, written in DocBook-XML, has been added.
* Rake has replaced the role of +make+. All makefiles have been
converted accordingly.
* The test generation tool now generates multiple files (runner,
bench, design, spec) and makes backups of existing files. See its
help information for details.
* Support for RSpec 0.5.4 has been added.
* The counter example now makes use of RSpec.
* Tested and developed using:
* Ruby 1.8.4 and Icarus Verilog 0.8 on i686 GNU/Linux
* Ruby 1.8.4 and Mentor Modelsim 6.1d on x86_64 GNU/Linux
== Acknowledgment
* Thanks to Jose Renau for solving the problem of strange delays
that occurred whenever a design was reset.
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