Analysis of the same path by two different tools in ISE yiel

M

MM

Guest
Analyze Timing / Floorplan Design with PlanAhead is using a different number
for total system jitter (TSJ) compared to Post-Place & Route Static Timing
Analysis yielding very different results... The PlanAhead seems to be more
conservative. Or does it know more about where the clock comes from? Also,
for some reason even being more conservative in my case it somehow reports
less number of errors... Perhaps it is not always more conservative...

Any comments?

Thanks,
/Mikhail
 
Actually, the difference seems to be not between PlanAhead and Post-Place &
Route Static Timing Analysis, but between different runs of the latter. In
one case it picks the TSJ from the top UCF file, in another case it inserts
some 70 ps instead...

The question still remains why PlanAhead reports a much smaller number of
errors than the Post-Place & Route Static Timing Analysis even though the
top errors are exactly the same... Is there are a hidden limit on the number
of errors reported in PlanAhead, which I can't find?

When I tried running Report Timing from PlanAhead it quietly crashed... :(


/Mikhail
 
On Thu, 21 Oct 2010 17:58:35 -0400, "MM" <mbmsv@yahoo.com> wrote:

The question still remains why PlanAhead reports a much smaller number of
errors than the Post-Place & Route Static Timing Analysis even though the
top errors are exactly the same... Is there are a hidden limit on the number
of errors reported in PlanAhead, which I can't find?
Given the name of the tool, is it reporting a prediction or estimate of the
timing errors rather than the actual placed and routed design?

If so, use it as guidance in the early stages, but once you have a routed
design, ignore it and pay attention to the Post-P&R results instead.

The important question is, why is your design not meeting post-P&R timing?

One hint: The placement phase starts from a randomised initial placement, and
refines it in multiple stages. But sometimes it yields a non-optimal result,
with one LUT or FF (or a few) wildly far away from its logical neighbours. This
placement is repeatable on subsequent runs. However, the least perturbation to
the design can disrupt the initial placement, and destroy a good design, or mend
a broken one...

Xilinx allow you to change the seed for this placement (via the "-t" switch to
MAP and PAR, or a GUI option) and this is a better way to perturb the placement.
(You need to supply the same seed, between 1 and 100, to BOTH tools, as of about
ISE9 or 10).

If your design is close (say 5-10%) to meeting timing, and there is no obvious
design problem in the error reports (long carry chains, or FFs that unexpectedly
migrated into IOBs or multipliers, and therefore moved a long way from your
logic), it is well worth re-running MAP and PAR with a different seed (or a few)
before trying anything else.

When I tried running Report Timing from PlanAhead it quietly crashed... :(
There are usually ways of quietly crashing the Xilinx tools. Learning how to
avoid the minefields (and ideally, reporting them, if they are reproducible) is
one of the bigger tasks.
 
"Brian Drummond" <brian_drummond@btconnect.com> wrote in message
news:dih2c61d7fg70b1l87dgjlp6rrt9rhqv7a@4ax.com...
On Thu, 21 Oct 2010 17:58:35 -0400, "MM" <mbmsv@yahoo.com> wrote:


The question still remains why PlanAhead reports a much smaller number of
errors than the Post-Place & Route Static Timing Analysis even though the
top errors are exactly the same... Is there are a hidden limit on the
number
of errors reported in PlanAhead, which I can't find?

Given the name of the tool, is it reporting a prediction or estimate of
the
timing errors rather than the actual placed and routed design?

If so, use it as guidance in the early stages, but once you have a routed
design, ignore it and pay attention to the Post-P&R results instead.
The name of the tool might be confusing. However, in the latest Xilinx
toolset it can used, among other things, for post-P&R timing analysis. And I
should add that it has a very nice and convenient interface for that. The
errors are not estimates, but the actual routed paths. However, it doesn't
display the paths as routed, which is a little annoying.


/Mikhail
 
On Oct 22, 9:38 am, "MM" <mb...@yahoo.com> wrote:
"Brian Drummond" <brian_drumm...@btconnect.com> wrote in message

news:dih2c61d7fg70b1l87dgjlp6rrt9rhqv7a@4ax.com...

On Thu, 21 Oct 2010 17:58:35 -0400, "MM" <mb...@yahoo.com> wrote:

The question still remains why PlanAhead reports a much smaller number of
errors than the Post-Place & Route Static Timing Analysis even though the
top errors are exactly the same... Is there are a hidden limit on the
number
of errors reported in PlanAhead, which I can't find?

Given the name of the tool, is it reporting a prediction or estimate of
the
timing errors rather than the actual placed and routed design?

If so, use it as guidance in the early stages, but once you have a routed
design, ignore it and pay attention to the Post-P&R results instead.

The name of the tool might be confusing. However, in the latest Xilinx
toolset it can used, among other things, for post-P&R timing analysis. And I
should add that it has a very nice and convenient interface for that. The
errors are not estimates, but the actual routed paths. However, it doesn't
display the paths as routed, which is a little annoying.

/Mikhail
You can see the routing if you open the design in the FPGA editor.
You can also
cross-probe to the FPGA editor from the post P&R timing report if you
use
the ISE GUI. FPGA editor also shows delays to each load for a
selected net.

Regards,
Gabor
 
"Gabor" <gabor@alacron.com> wrote in message
news:c8ba2148-1052-4627-99d6-9ba961ba5408@i5g2000yqe.googlegroups.com...
You can see the routing if you open the design in the FPGA editor.
You can also cross-probe to the FPGA editor from the post P&R timing report
if you
use the ISE GUI. FPGA editor also shows delays to each load for a selected
net.
Yes, thanks, I know all that. The PlanAhead just does some of that nicer by
combining comprehensive device view with the timing report.

/Mikhail
 
"Gabor" <gabor@alacron.com> wrote

Well, I haven't really touched plan-ahead. Then again, I never used PACE
or the old floorplanner either, so I'm more comfortable with the FPGA
editor.
But I've never seen the FPGA editor numbers disagree with the timing
report either.
Give it a try. It's easy. If you have a project in ISE (I am currently using
the latest 12.3), in the processes view, under Place & Route you'll see
Analyze Timing / Floorplan Design (PlanAhead). This will open your routed
design in PlanAhead. Note that PlanAhead greys out certain functions
depending on where it is open from. To see its full power you need to open
it standalone and create a project. I actually think that Xilinx might one
day replace ISE front-end with PlanAhead, it feels like a better organized
and more powerful GUI. Although, I haven't used it much yet, and haven't
tried RTL flow at all, so I might be wrong. What I like in it is how easy it
is to create multiple jobs, launch them all and compare the results. Here is
how I used it the most so far: I would synthesize the project in ISE, and
then create a standalone netlist project in PlanAhead. After that you can
create and launch multiple map/par strategies with a few mouse clicks.


/Mikhail
 
On Oct 22, 4:04 pm, "MM" <mb...@yahoo.com> wrote:
"Gabor" <ga...@alacron.com> wrote in message

news:c8ba2148-1052-4627-99d6-9ba961ba5408@i5g2000yqe.googlegroups.com...



You can see the routing if you open the design in the FPGA editor.
You can also cross-probe to the FPGA editor from the post P&R timing report
if you
use the ISE GUI.  FPGA editor also shows delays to each load for a selected
net.

Yes, thanks, I know all that. The PlanAhead just does some of that nicer by
combining comprehensive device view with the timing report.

/Mikhail
Well, I haven't really touched plan-ahead. Then again, I never used
PACE
or the old floorplanner either, so I'm more comfortable with the FPGA
editor.
But I've never seen the FPGA editor numbers disagree with the timing
report either.

Regards,
Gabor
 

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