S
Shiv
Guest
dear friends,
I have synthesized and simulated a verilog code in cadence, after
synthesizing the code i need to analyse the time delay and power
lossess, please guide me how to do this and which command will be used
in this, I have read its manual SETTING CONSTRAINTS AND PERFORMING
TIMING ANALYSIS USING ENCOUNTER RTL COMPILER, but could not understand
it, please help me
Thanking in advance
Shiv Gopal
I have synthesized and simulated a verilog code in cadence, after
synthesizing the code i need to analyse the time delay and power
lossess, please guide me how to do this and which command will be used
in this, I have read its manual SETTING CONSTRAINTS AND PERFORMING
TIMING ANALYSIS USING ENCOUNTER RTL COMPILER, but could not understand
it, please help me
Thanking in advance
Shiv Gopal