analog layout

[jutek]

hello

i'm doing an analog layout using skill procedures and pcells.
it should work with any technology so it can be a problem with grid.

in analog layout i use many contacts so how to write procedures to work
with different grid's

regards

 

[vdvalk@rogers.com]

Sorry. but this post seems somewhat unfocused to me.

Doing analog layout with skill procedures is not an effective use of
time.

Pcells that are technology independant is another issue. Some success
can be found here by using generic Pcells that are either Technology
file based or "Q-Cell" based will help with generic layouts. The
problem is that any "skilled" (pun intended) layout person will want to
customize at the device level to create a more efficent layout. (This
tends to mess up he interface into tools such as VXL ... )

Contacts are actually a special kind of pcell that must be dealt with
carefully.

The grid issue is best solved by working to the centers of contacts.
This is problematic in technologies that allow odd sized contacts and
wires.
(i.e. if we had a 0.05u grid and contacts were 0.45u wide, and wires
0.65u wide, then contacts or wire centers cannot be placed on grid!)

I think that the long term solution here would be to have a system
where the routine that places a device can return a value that
indicates the space/area
taken and that the placing function can then take action as required.

I have built and used skill systems that do this, but not in
interactive mode.

-- Gerry.

Note that Ciranova (www.ciranova.com) has a PYTHON based pcell
environment that is worth looking at. But it is OA (Open Access )
only!)

 

[jutek]

vdvalk@rogers.com wrote:

Sorry. but this post seems somewhat unfocused to me.

Doing analog layout with skill procedures is not an effective use of
time.

yeah, i know what you mean , but it's a special layout resized

and specified for any technology. i want this process to be automated,
cause it
repeates every time.

thanks and regards

 

[vdvalk@rogers.com]

I think you need to figure out what your logical grid is.

Then you need to map your starting technology to your target
technology.

Then you need to map each starting technology rule to an equivalent
target technology rule.
This step will likely be filled with inconsistencies.

The starting technology will have a physical grid of some dimension.
The target technology may have a different physical grid.

One solution is to scale a copy of your structures into the target
technology.

Then you need to adjust each rule/structure to fit into the new
technology
This step is filled with tradeoffs as you will have cases where the
target technology has larger or smaller constraints that
the starting technology. Sometime the solution here is to accept the
larger of the two. Other times you need to modify the
structure. Simple devices, interconnect. contacts can be mapped fairly
quickly. Complex structures may require complex rewrites.

Once you have mapped into a few of each style of
device/technology/structure then the process can become almost
automated,
but special cases seem to come up.

I found that somestructures were tricky. I/O structures often do not
scale with the rest of the process as some of the physics of them
require constant size.
Sensitive analog circuits are also problematic as some noise issues do
not scale well.

Straight CMOS and voltage devices ( Resistors, Capacitors) scale ok,
but Bipolars and Current sensitive devices are usually somewhat
non-linear and require some sophisticated tuning to get close to the
right kind of translation.

I have had considerable success in mapping CMOS logic from 0.5u -> 0.4u
-> 0.3u -> 0.25u -> .18u -> .15u -> 0.13u ... 90nm AND 65nm were
problematic due to DFM requirements.

Some bipolar circuits can be scaled in a limited way, but require very
careful checking that the ccts. are still close to their optimal
operational ranges.

YMMV

-- Gerry