Analog Environment - Subcircuit degeneration - incorrect nod

[circuit student]

Hi,

This is probably an easy problem, but I asked around and noone seemed
to know whats wrong.

So, very simple: I made a NAND gate out of 4 standard analog
transistors in Composer-Schematic, and generated a symbol from it. I
named the vdd wire with 'wire name' of ' vdd! ', and the gnd wire with
'wire name' of ' gnd! '.

I made a new test cell-schematic, instantiated the NAND gate as a
symbol inside the test schematic, and added some voltage sources for
VDD and inputs, and a capacitor on the output.

Analog environment generates the appropriate HSPICE deck, but the
subcircuit definition it generates for my NAND gate has all the 'vdd! '
and 'gnd!' nodes named as node '3' and '5'.

I even tried using 'net expressions' to name the vdd and gnd nodes in
my NAND, but it didn't work. The only way I got past this was copying
and pasting the entire NAND gate into my test schematic.

NOTE: I did make a NAND layout, DRC'ed and LVS'ed with the schematic,
then I extracted parasitic capacitances and backannotated onto the
schematic (so Analog Environment used the extracted parasitics to add a
bunch of parasitic caps to my SPICE deck).



Thanks for any help,
A troubled student

 

[Poojan Wagh]

I can't give you the full explanation (you'll want to consult cadence
docs), but if you define a global port, it has an exclamation point
after it. Maybe Cadence is getting confused, thinking that vdd! and
vss! are globals. Try changing your NAND to not have the ! point and
see if it helps.

circuit student wrote:

Hi,

This is probably an easy problem, but I asked around and noone seemed
to know whats wrong.

So, very simple: I made a NAND gate out of 4 standard analog
transistors in Composer-Schematic, and generated a symbol from it. I
named the vdd wire with 'wire name' of ' vdd! ', and the gnd wire with
'wire name' of ' gnd! '.

I made a new test cell-schematic, instantiated the NAND gate as a
symbol inside the test schematic, and added some voltage sources for
VDD and inputs, and a capacitor on the output.

Analog environment generates the appropriate HSPICE deck, but the
subcircuit definition it generates for my NAND gate has all the 'vdd! '
and 'gnd!' nodes named as node '3' and '5'.

I even tried using 'net expressions' to name the vdd and gnd nodes in
my NAND, but it didn't work. The only way I got past this was copying
and pasting the entire NAND gate into my test schematic.

NOTE: I did make a NAND layout, DRC'ed and LVS'ed with the schematic,
then I extracted parasitic capacitances and backannotated onto the
schematic (so Analog Environment used the extracted parasitics to add a
bunch of parasitic caps to my SPICE deck).



Thanks for any help,
A troubled student

 

[circuit student]

Hello,

Thanks for your reply.

Actually, I tried many permutations of renaming stuff. So, I renamed
the vdd! and gnd! in my NAND to vdd and gnd.

In my test schematic, I then connected to the vdd and gnd supply nets I
instantiated from the analog library to wires named vdd and gnd.

Cadence then gave me the error that "vdd! is shorted to vdd" and "gnd!
is shorted to gnd".

Weird stuff...

Best,
circuit student


Poojan Wagh wrote:

I can't give you the full explanation (you'll want to consult cadence
docs), but if you define a global port, it has an exclamation point
after it. Maybe Cadence is getting confused, thinking that vdd! and
vss! are globals. Try changing your NAND to not have the ! point and
see if it helps.

circuit student wrote:
Hi,

This is probably an easy problem, but I asked around and noone seemed
to know whats wrong.

So, very simple: I made a NAND gate out of 4 standard analog
transistors in Composer-Schematic, and generated a symbol from it. I
named the vdd wire with 'wire name' of ' vdd! ', and the gnd wire with
'wire name' of ' gnd! '.

I made a new test cell-schematic, instantiated the NAND gate as a
symbol inside the test schematic, and added some voltage sources for
VDD and inputs, and a capacitor on the output.

Analog environment generates the appropriate HSPICE deck, but the
subcircuit definition it generates for my NAND gate has all the 'vdd! '
and 'gnd!' nodes named as node '3' and '5'.

I even tried using 'net expressions' to name the vdd and gnd nodes in
my NAND, but it didn't work. The only way I got past this was copying
and pasting the entire NAND gate into my test schematic.

NOTE: I did make a NAND layout, DRC'ed and LVS'ed with the schematic,
then I extracted parasitic capacitances and backannotated onto the
schematic (so Analog Environment used the extracted parasitics to add a
bunch of parasitic caps to my SPICE deck).



Thanks for any help,
A troubled student

 

[BEE]

Add netSet property to your symbol to connect the simulation pwr/gnd net
names to the net expression.
shift+q -> Add -> <name of your property> netSet <power name on
simulation schematic>


"circuit student" <jigglysnot@gmail.com> wrote in message
news:1158298809.484129.131780@p79g2000cwp.googlegroups.com...

Hello,

Thanks for your reply.

Actually, I tried many permutations of renaming stuff. So, I renamed
the vdd! and gnd! in my NAND to vdd and gnd.

In my test schematic, I then connected to the vdd and gnd supply nets I
instantiated from the analog library to wires named vdd and gnd.

Cadence then gave me the error that "vdd! is shorted to vdd" and "gnd!
is shorted to gnd".

Weird stuff...

Best,
circuit student


Poojan Wagh wrote:
I can't give you the full explanation (you'll want to consult cadence
docs), but if you define a global port, it has an exclamation point
after it. Maybe Cadence is getting confused, thinking that vdd! and
vss! are globals. Try changing your NAND to not have the ! point and
see if it helps.

circuit student wrote:
Hi,

This is probably an easy problem, but I asked around and noone seemed
to know whats wrong.

So, very simple: I made a NAND gate out of 4 standard analog
transistors in Composer-Schematic, and generated a symbol from it. I
named the vdd wire with 'wire name' of ' vdd! ', and the gnd wire with
'wire name' of ' gnd! '.

I made a new test cell-schematic, instantiated the NAND gate as a
symbol inside the test schematic, and added some voltage sources for
VDD and inputs, and a capacitor on the output.

Analog environment generates the appropriate HSPICE deck, but the
subcircuit definition it generates for my NAND gate has all the 'vdd! '
and 'gnd!' nodes named as node '3' and '5'.

I even tried using 'net expressions' to name the vdd and gnd nodes in
my NAND, but it didn't work. The only way I got past this was copying
and pasting the entire NAND gate into my test schematic.

NOTE: I did make a NAND layout, DRC'ed and LVS'ed with the schematic,
then I extracted parasitic capacitances and backannotated onto the
schematic (so Analog Environment used the extracted parasitics to add a
bunch of parasitic caps to my SPICE deck).



Thanks for any help,
A troubled student