an unadulterated question

[Rafal Pietrak]

Hi!

Xilinx XST just barked at me:
--------------------------from *.syr---------------------
ERROR:Xst:2070 - If you are attempting to describe a dual-port
block RAM with two separate write ports for signal <rf>, please
use a shared variable instead. Coding guidelines are provided
in the user manual.
--------------------------------------------------------

While I've only said:
-----------------------my *.vhd--------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rfile is
generic ( WORD_SIZE : natural := 4; ADDR_BITS : natural := 6);
Port ( data: inout std_logic_vector(WORD_SIZE-1 downto 0);
addr: in std_logic_vector(ADDR_BITS-1 downto 0);
datab: inout std_logic_vector(WORD_SIZE-1 downto 0);
addrb: in std_logic_vector(ADDR_BITS-1 downto 0);
wr2,rd2: in std_logic;
rd,wr: in std_logic);
end rfile;

architecture rtl of rfile is
type rft is array((2**ADDR_BITS)-1 downto 0) of
std_logic_vector(WORD_SIZE-1 downto 0);

signal rf: rft;

begin
process(wr)
begin
if rising_edge(wr) then
rf(CONV_INTEGER(addr)) <= data;
end if;
end process;

process(wr2)
begin
if rising_edge(wr2) then
rf(CONV_INTEGER(addrb)) <= datab;
end if;
end process;

data <= (others => 'Z') when (wr = '0') or (rd = '1') else
rf(CONV_INTEGER(addr));
datab <= (others => 'Z') when (wr2 = '0') or (rd2 = '1') else
rf(CONV_INTEGER(addrb));

end rtl;
-----------------------------------------------------

Now, I think Xilinx should teach that beast a little politeness, here

But seriously.

YES!! I really did mean "writable dual ported RAM" here. I really don't
understand, why the synthesizer could recognize my intention and
*at*the*same*time* faulted to create what it's been asked for?!?!?!

So; Would someone be kind enough and tell me which volume (and paged
XST is referring to?

Of course if it's really a 'common construct', which is know by heart for
all you engineers - pls, pls just post a code snippet. The 'Language
Templates' within Xilinx ISE, regrettably don't contain "dual ported RAM
with two writable channels".

I'd really appreciate any help here.

-R

PS: to a Xilinx reader - politeness here is putting a referral (like URL)
inside this already long ERROR message. ERROR message in it's current
form means nothing to a novice (like myself), and at the same time is
probably over talkative for an experienced engineer. Thank you.

 

[jens]

You're using two separate processes to assign the same signal, which is
why it wants you to use a shared variable, which allows two separate
processes to write to the same variable (even though what happens when
you simultaneously write to the same memory location is undefined).

 

[Rafal Pietrak]

On Wed, 05 Apr 2006 06:34:38 -0700, jens wrote:

You're using two separate processes to assign the same signal, which is
why it wants you to use a shared variable, which allows two separate
processes to write to the same variable (even though what happens when
you simultaneously write to the same memory location is undefined).

Pure magic!!

Thank you for this info. I'm able to go forward, now.

PS: I should have tried the shared variables before the posting, but It
looked to me more like a kind of unimaginable synthesizer fault then a
real problem in my source - without this hint on concurrent updates.