A
analog
Guest
--- In LTspice@yahoogroups.com, Dennis wrote:
Here's what I've come up with. It's simple, fast and seems to be a
reasonable match to the data sheet for gain, charge and switching.
* SGN20N40L.sub by analog, rev. 1 August 7th 2004
* - - - - - - - - C G E
..subckt SGN20N40L 1 2 3
M1 4 2 3 Qi
Q1 3 4 1 Qo
..model Qi vdmos(Rg=3 Rs=1.6 Vto=1.2 Kp=22 Is=0 ; static effects
+ Cgdmax=8n Cgdmin=10p Cgs=4n Cjo=1n) ; dynamic effects
..model Qo pnp(Is=5u Nf=2.7 Bf=150 Rb=0.5 Ikf=200 ; static effects
+ Trb1=18m Eg=.75 Xtb=-.25 ; temperature effects
+ Cjc=1n Cje=0.3n tf=5n) ; dynamic effects
..ends SGN20N40L
This model is nothing more than an N-channel mosfet driving a pnp bjt.
It could be placed on a schematic as an explicit mosfet-bjt compound
pair along with a SPICE directive (text) containing the two corres-
ponding model statements, or it could be invoked as a subcircuit
coupled to LTspice's built-in NIGBT symbol (located in the "Misc"
symbol subfolder).
In an attempt to accurately capture switching behavior, gate charge
is modeled using LTspice's highly efficient custom VDMOS with its
convenient built-in nonlinear miller d-g capacitance, and storage time
tailing is added via the pnp's "tf" (transit time) parameter. Note
that for the VDMOS, "Is" has been set to zero in an attempt to disable
the body diode.
By leaving out certain (seemingly) unnecessary parameters, internal
device nodes have been kept to a minimum in the interests of quick
run times. If anyone uses this model (or a modified version of it),
please post a message to report unrealistic behavior or any other
simulation difficulties.
Like most spice models this one responds to the static global temp-
erature setting. Unfortunately, also like most spice models, this
one has no dynamic internal thermal feedback. Looking at the stepped
gate drive family of output curves from the data sheet, it seems
local die heating causes the normally constant current portion of
the curves to bend down as voltage and dissipation rise (probably
due to the inverse temperature dependence of junction voltage). By
the basic physics of the device I believe these lines would slope up
slightly were it not for the dynamic temperature rise. Adding the
parameter Lambda=50m (or there abouts) to the VDMOS model would add
this effect if it proved important to near-isothermic pulsed
applications. -- analog
A nearly native IGBT model would be a worthwhile addition to LTspice.
Here's what I've come up with. It's simple, fast and seems to be a
reasonable match to the data sheet for gain, charge and switching.
* SGN20N40L.sub by analog, rev. 1 August 7th 2004
* - - - - - - - - C G E
..subckt SGN20N40L 1 2 3
M1 4 2 3 Qi
Q1 3 4 1 Qo
..model Qi vdmos(Rg=3 Rs=1.6 Vto=1.2 Kp=22 Is=0 ; static effects
+ Cgdmax=8n Cgdmin=10p Cgs=4n Cjo=1n) ; dynamic effects
..model Qo pnp(Is=5u Nf=2.7 Bf=150 Rb=0.5 Ikf=200 ; static effects
+ Trb1=18m Eg=.75 Xtb=-.25 ; temperature effects
+ Cjc=1n Cje=0.3n tf=5n) ; dynamic effects
..ends SGN20N40L
This model is nothing more than an N-channel mosfet driving a pnp bjt.
It could be placed on a schematic as an explicit mosfet-bjt compound
pair along with a SPICE directive (text) containing the two corres-
ponding model statements, or it could be invoked as a subcircuit
coupled to LTspice's built-in NIGBT symbol (located in the "Misc"
symbol subfolder).
In an attempt to accurately capture switching behavior, gate charge
is modeled using LTspice's highly efficient custom VDMOS with its
convenient built-in nonlinear miller d-g capacitance, and storage time
tailing is added via the pnp's "tf" (transit time) parameter. Note
that for the VDMOS, "Is" has been set to zero in an attempt to disable
the body diode.
By leaving out certain (seemingly) unnecessary parameters, internal
device nodes have been kept to a minimum in the interests of quick
run times. If anyone uses this model (or a modified version of it),
please post a message to report unrealistic behavior or any other
simulation difficulties.
Like most spice models this one responds to the static global temp-
erature setting. Unfortunately, also like most spice models, this
one has no dynamic internal thermal feedback. Looking at the stepped
gate drive family of output curves from the data sheet, it seems
local die heating causes the normally constant current portion of
the curves to bend down as voltage and dissipation rise (probably
due to the inverse temperature dependence of junction voltage). By
the basic physics of the device I believe these lines would slope up
slightly were it not for the dynamic temperature rise. Adding the
parameter Lambda=50m (or there abouts) to the VDMOS model would add
this effect if it proved important to near-isothermic pulsed
applications. -- analog