an error to be corrected

[guide]

i am writing a simple verilog program to see the project navigator 6.1
editon. the behavoiral simulation is fine. but give me an error when i am
simulating the post layout and post translate. it says unresolved
reference to state s0 and s1. can u please guide me.

module addition(A,B,clk,C,rst);
input A;
input B;
input clk;
input rst;
output C;

reg C;
reg [1:0] state;
reg [1:0] next_state;
reg next_C;
reg next_A;
reg next_B;
reg next_start;
reg start;


parameter[1:0] S0 = 2'b01;
parameter [1:0] S1 = 2'b10;

always @ (posedge clk or negedge rst)
begin
if (~ rst)
begin
C <= 0;
start <= 1;
state <= S0;
end
else
begin
start <= 0;
C <= next_C;
state <= next_state;
end
end

always @(state or start or next_A or next_B or next_C or C or A
or B)
begin
case (state)

S0:begin
if(start == 0)
begin
next_C = 0;
next_B = 0;
next_A = 0;
next_state = S0;
end
else
begin
next_C = C;
next_B = B;
next_state = S1;
end
end


S1:
begin
next_C = A * B;
next_state = S0;
next_start = 0;
end

default : begin
next_state = S0;
end
endcase
end

endmodule

 

[Neo]

I dont any problem in the code.
But remember verilog is case sensitive and your error is about 's0' and
's1' not ' S0' and 'S1'.